| Analysis and characterization of inherent application resilience for approximate computing VK Chippa, ST Chakradhar, K Roy, A Raghunathan Proceedings of the 50th Annual Design Automation Conference, 1-9, 2013 | 641 | 2013 |
| Quality programmable vector processors for approximate computing S Venkataramani, VK Chippa, ST Chakradhar, K Roy, A Raghunathan Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 349 | 2013 |
| Design of voltage-scalable meta-functions for approximate computing D Mohapatra, VK Chippa, A Raghunathan, K Roy 2011 Design, Automation & Test in Europe, 1-6, 2011 | 279 | 2011 |
| Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency VK Chippa, D Mohapatra, A Raghunathan, K Roy, ST Chakradhar Proceedings of the 47th Design Automation Conference, 555-560, 2010 | 240 | 2010 |
| Scalable effort hardware design VK Chippa, D Mohapatra, K Roy, ST Chakradhar, A Raghunathan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (9 …, 2014 | 133 | 2014 |
| Approximate computing: An integrated hardware approach VK Chippa, S Venkataramani, ST Chakradhar, K Roy, A Raghunathan 2013 Asilomar conference on signals, systems and computers, 111-117, 2013 | 92 | 2013 |
| Dynamic effort scaling: Managing the quality-efficiency tradeoff V Chippa, A Raghunathan, K Roy, S Chakradhar Proceedings of the 48th Design Automation Conference, 603-608, 2011 | 66 | 2011 |
| StoRM: A stochastic recognition and mining processor VK Chippa, S Venkataramani, K Roy, A Raghunathan Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 46 | 2014 |
| Managing the quality vs. efficiency trade-off using dynamic effort scaling VK Chippa, K Roy, ST Chakradhar, A Raghunathan ACM Transactions on Embedded Computing Systems (TECS) 12 (2s), 1-23, 2013 | 18 | 2013 |
| Energy-efficient recognition and mining processor using scalable effort design VK Chippa, H Jayakumar, D Mohapatra, K Roy, A Raghunathan Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 17 | 2013 |
| Energy efficient many-core processor for recognition and mining using spin-based memory R Venkatesan, VK Chippa, C Augustine, K Roy, A Raghunathan 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 122-128, 2011 | 16 | 2011 |
| Domain-specific many-core computing using spin-based memory R Venkatesan, VK Chippa, C Augustine, K Roy, A Raghunathan IEEE Transactions on Nanotechnology 13 (5), 881-894, 2014 | 12 | 2014 |
| Scalable effort hardware VK Chippa | 1 | 2013 |
| Tor M. Aamodt 99, 408 Mohamad Abdel-Majeed 111 Jaume Abella 160 Jorge Albericio 310 H Ando, M Annavaram, R Ausavarungnirun, R Balasubramanian, ... | | |
Anand RaghunathanProfessor of Electrical and Computer Engineering, Purdue UniversityPotvrđena adresa e-pošte na purdue.edu
