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Dr. Harsupreet kaur
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Year
An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET
H Kaur, S Kabra, S Haldar, RS Gupta
Microelectronics Journal 38 (3), 352-359, 2007
592007
Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability
H Kaur, S Kabra, S Bindra, S Haldar, RS Gupta
Solid-state electronics 51 (3), 398-404, 2007
592007
An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET
H Kaur, S Kabra, S Haldar, RS Gupta
Solid-state electronics 52 (2), 305-311, 2008
362008
Modeling and simulation study of novel Double Gate Ferroelectric Junctionless (DGFJL) transistor
H Mehta, H Kaur
Superlattices and microstructures 97, 536-547, 2016
352016
Impact of Gaussian doping profile and negative capacitance effect on double-gate junctionless transistors (DGJLTs)
H Mehta, H Kaur
IEEE Transactions on Electron Devices 65 (7), 2699-2706, 2018
332018
Two-dimensional subthreshold analysis of sub-micron GaN MESFET
S Kabra, H Kaur, S Haldar, M Gupta, RS Gupta
Microelectronics journal 38 (4-5), 547-555, 2007
292007
Temperature dependent analytical model of sub-micron GaN MESFETs for microwave frequency applications
S Kabra, H Kaur, S Haldar, M Gupta, RS Gupta
Solid-state electronics 52 (1), 25-30, 2008
252008
Study on impact of parasitic capacitance on performance of graded channel negative capacitance SOI FET at high temperature
H Mehta, H Kaur
IEEE Transactions on Electron Devices 66 (7), 2904-2909, 2019
222019
Analysis of negative-capacitance germanium finfet with the presence of fixed trap charges
M Bansal, H Kaur
IEEE Transactions on Electron Devices 66 (4), 1979-1984, 2019
202019
A semi empirical approach for submicron GaN MESFET using an accurate velocity field relationship for high power applications
S Kabra, H Kaur, R Gupta, S Haldar, M Gupta, RS Gupta
Microelectronics journal 37 (7), 620-626, 2006
202006
Improved temperature resilience and device performance of negative capacitance reconfigurable field effect transistors
P Pandey, H Kaur
IEEE Transactions on Electron Devices 67 (2), 738-744, 2020
112020
High temperature performance of Si: HfO2 based long channel double gate ferroelectric junctionless transistors
H Mehta, H Kaur
Superlattices and Microstructures 103, 78-84, 2017
112017
Impact of negative capacitance effect on germanium double gate pFET for enhanced immunity to interface trap charges
M Bansal, H Kaur
Superlattices and Microstructures 117, 189-199, 2018
102018
Performance and sensitivity analysis of polarity controllable-ion sensitive FET for pH sensing applications
P Pandey, H Kaur
Silicon 14 (14), 8467-8474, 2022
82022
Implementing variable doping and work function engineering in β-Ga2O3 MOSFET to realize high breakdown voltage and PfoM
P Goyal, H Kaur
Semiconductor Science and Technology 37 (4), 045018, 2022
82022
Subthreshold analytical model for dual-material double gate ferroelectric field effect transistor (DMGFeFET)
H Mehta, H Kaur
Semiconductor Science and Technology 34 (6), 065008, 2019
82019
An analytical model for GaN MESFET's using new velocity‐field dependence
S Kabra, H Kaur, S Haldar, M Gupta, RS Gupta
physica status solidi c 3 (6), 2350-2355, 2006
82006
Superior performance and reliability of double gate Gaussian doped negative capacitance junctionless transistor for 200–500 K
H Mehta, H Kaur
IETE Technical Review 37 (4), 391-401, 2020
72020
Performance assessment of symmetric double gate negative capacitance junctionless transistor with high-k spacer at elevated temperatures
H Mehta, H Kaur
Advances in Natural Sciences: Nanoscience and Nanotechnology 10 (3), 035013, 2019
72019
Impact of interface layer and metal workfunction on device performance of ferroelectric junctionless cylindrical surrounding gate transistors
H Mehta, H Kaur
Superlattices and Microstructures 111, 194-205, 2017
52017
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Articles 1–20