A soft dual-processor system with a partially run-time reconfigurable shared 128-bit SIMD engine JRG Ordaz, D Koch 2018 IEEE 29th international conference on application-specific systems …, 2018 | 9 | 2018 |
soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric JRG Ordaz, D Koch 2016 IEEE 27th International Conference on Application-specific Systems …, 2016 | 7 | 2016 |
A reorder buffer design for high performance processors JRG Ordaz, MAR Salinas, LAV Vargas, HM Lozano, CP Macías Computación y Sistemas 16 (1), 15-25, 2012 | 7 | 2012 |
A security library for FPGA interlays A Vaishnav, JRG Ordaz, D Koch 2017 27th International Conference on Field Programmable Logic and …, 2017 | 4 | 2017 |
On the hls design of bit-level operations and custom data types JRG Ordaz, D Koch FSP 2017; Fourth International Workshop on FPGAs for Software Programmers, 1-8, 2017 | 3 | 2017 |
Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit JRG Ordaz, D Koch 2017 27th International Conference on Field Programmable Logic and …, 2017 | 3 | 2017 |
Diseño de un rob-distribuido para procesadores superescalares JRG Ordaz Instituto Politécnico Nacional, 2010 | 3* | 2010 |
HLS compilation for CPU interlays JRG Ordaz, D Koch Proceedings of the 8th International Symposium on Highly Efficient …, 2017 | 1 | 2017 |
DYNAMIC CPU ISA CUSTOMIZATIONS THROUGH FPGA INTERLAYS JR Garcia Ordaz https://www.research.manchester.ac.uk/portal/en/theses/dynamic-cpu-isa …, 2018 | | 2018 |
Diseño de un búfer de reordenamiento para procesadores de alto desempeño JR García Ordaz, MA Ramírez Salinas, LA Villa Vargas, H Molina Lozano, ... Computación y Sistemas 16 (1), 15-25, 2012 | | 2012 |