Yutaka Nakamura
Yutaka Nakamura
IBM Research - Tokyo (IBM Japan)
Verified email at - Homepage
Cited by
Cited by
A million spiking-neuron integrated circuit with a scalable communication network and interface
PA Merolla, JV Arthur, R Alvarez-Icaza, AS Cassidy, J Sawada, ...
Science 345 (6197), 668-673, 2014
Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip
F Akopyan, J Sawada, A Cassidy, R Alvarez-Icaza, J Arthur, P Merolla, ...
IEEE transactions on computer-aided design of integrated circuits and …, 2015
An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches
L Chang, RK Montoye, Y Nakamura, KA Batson, RJ Eickemeyer, ...
IEEE Journal of Solid-State Circuits 43 (4), 956-963, 2008
A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65nm CMOS
L Chang, Y Nakamura, RK Montoye, J Sawada, AK Martin, K Kinoshita, ...
2007 IEEE Symposium on VLSI Circuits, 252-253, 2007
Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with~ 100× speedup in time-to-solution and~ 100,000× reduction in energy-to-solution
AS Cassidy, R Alvarez-Icaza, F Akopyan, J Sawada, JV Arthur, ...
SC'14: Proceedings of the International Conference for High Performance …, 2014
A 14 nm embedded stt-mram cmos technology
D Edelstein, M Rizzolo, D Sil, A Dutta, J DeBrosse, M Wordeman, A Arceo, ...
2020 IEEE International Electron Devices Meeting (IEDM), 11.5. 1-11.5. 4, 2020
A 4R2W register file for a 2.3 GHz wire-speed POWER™ processor with double-pumped write operation
GS Ditlow, RK Montoye, SN Storino, SM Dance, S Ehrenreich, ...
2011 IEEE International Solid-State Circuits Conference, 256-258, 2011
An eight-bit prefetch circuit for high-bandwidth DRAM's
T Sunaga, K Hosokawa, Y Nakamura, M Ichinose, Y Igarashi
IEEE Journal of Solid-State Circuits 32 (1), 105-110, 1997
A full bit prefetch architecture for synchronous DRAM's
T Sunaga, K Hosokawa, Y Nakamura, M Ichinose, A Moriwaki, S Kakimi, ...
IEEE Journal of Solid-State Circuits 30 (9), 998-1005, 1995
Neural inference at the frontier of energy, space, and time
DS Modha, F Akopyan, A Andreopoulos, R Appuswamy, JV Arthur, ...
Science 382 (6668), 329-335, 2023
Dynamic semiconductor storage device and method for operating same
Y Nakamura
US Patent 7,616,510, 2009
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing
J DeBrosse, T Maffitt, Y Nakamura, G Jan, PK Wang
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-3, 2015
Spin-torque transfer magneto-resistive memory architecture
JK DeBrosse, Y Nakamura
US Patent 8,446,757, 2013
Ultra high-speed Nor-type LSDL/Domino combined address decoder
RK Montoye, Y Nakamura
US Patent 7,349,288, 2008
Dynamic semiconductor memory device and bit line precharge method therefor
Y Nakamura, T Sunaga
US Patent 6,944,076, 2005
A double-data-rate 2 (DDR2) interface phase-change memory with 533MB/s read-write data rate and 37.5 ns access latency for memory-type storage class memory applications
HL Lung, CP Miller, CJ Chen, SC Lewis, J Morrish, T Perri, RC Jordan, ...
2016 IEEE 8th International Memory Workshop (IMW), 1-5, 2016
Digital STDP synapse and LIF neuron-based neuromorphic system
T Yasuda, K Hosokawa, Y Nakamura, J Okazawa, M Ishii
US Patent 10,552,731, 2020
Hybrid static and dynamic sensing for memory arrays
L Chang, RK Montoye, Y Nakamura
US Patent 7,668,024, 2010
Dynamic semiconductor storage device and method of reading and writing operations thereof
Y Nakamura
US Patent 6,954,389, 2005
Cascode complimentary dual level shifter
JK DeBrosse, Y Nakamura
US Patent 10,115,450, 2018
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