| Ara: A 1-GHz+ scalable and energy-efficient RISC-V vector processor with multiprecision floating-point support in 22-nm FD-SOI M Cavalcante, F Schuiki, F Zaruba, M Schaffner, L Benini IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (2), 530-543, 2019 | 124 | 2019 |
| A scalable near-memory architecture for training deep neural networks on large in-memory datasets F Schuiki, M Schaffner, FK Gürkaynak, L Benini IEEE Transactions on Computers 68 (4), 484-497, 2018 | 101 | 2018 |
| FPnew: An open-source multiformat floating-point unit architecture for energy-proportional transprecision computing S Mach, F Schuiki, F Zaruba, L Benini IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 774-787, 2020 | 99 | 2020 |
| Manticore: A 4096-core RISC-V chiplet architecture for ultraefficient floating-point computing F Zaruba, F Schuiki, L Benini IEEE Micro 41 (2), 36-42, 2020 | 74 | 2020 |
| Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads F Zaruba, F Schuiki, T Hoefler, L Benini IEEE Transactions on Computers 70 (11), 1845-1860, 2020 | 66 | 2020 |
| LLHD: A multi-level intermediate representation for hardware description languages F Schuiki, A Kurth, T Grosser, L Benini Proceedings of the 41st ACM SIGPLAN Conference on Programming Language …, 2020 | 66 | 2020 |
| Stream semantic registers: A lightweight risc-v isa extension achieving full compute utilization in single-issue cores F Schuiki, F Zaruba, T Hoefler, L Benini IEEE Transactions on Computers 70 (2), 212-227, 2020 | 51 | 2020 |
| An open-source platform for high-performance non-coherent on-chip communication A Kurth, W Rönninger, T Benz, M Cavalcante, F Schuiki, F Zaruba, ... IEEE Transactions on Computers 71 (8), 1794-1809, 2021 | 48 | 2021 |
| MLIR as hardware compiler infrastructure S Eldridge, P Barua, A Chapyzhenka, A Izraelevitz, J Koenig, C Lattner, ... Workshop on Open-Source EDA Technology (WOSET) 3, 2021 | 28 | 2021 |
| A 0.80 pJ/flop, 1.24 Tflop/sW 8-to-64 bit transprecision floating-point unit for a 64 bit RISC-V processor in 22nm FD-SOI S Mach, F Schuiki, F Zaruba, L Benini 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 15 | 2019 |
| Indirection stream semantic register architecture for efficient sparse-dense linear algebra P Scheffler, F Zaruba, F Schuiki, T Hoefler, L Benini 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 14 | 2021 |
| The floating point trinity: A multi-modal approach to extreme energy-efficiency and performance F Zaruba, F Schuiki, S Mach, L Benini 2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019 | 12 | 2019 |
| NTX: An energy-efficient streaming accelerator for floating-point generalized reduction workloads in 22 nm FD-SOI F Schuiki, M Schaffner, L Benini 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 662-667, 2019 | 12 | 2019 |
| Banshee: A fast LLVM-based RISC-V binary translator S Riedel, F Schuiki, P Scheffler, F Zaruba, L Benini 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 10 | 2021 |
| Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems M Cavalcante, A Kurth, F Schuiki, L Benini Proceedings of the 17th ACM International Conference on Computing Frontiers …, 2020 | 10 | 2020 |
| A 4096-core RISC-V chiplet architecture for ultra-efficient floating-point computing F Zaruba, F Schuiki, L Benini 2020 IEEE Hot Chips 32 Symposium (HCS), 1-24, 2020 | 9 | 2020 |
| Sparse stream semantic registers: A lightweight ISA extension accelerating general sparse linear algebra P Scheffler, F Zaruba, F Schuiki, T Hoefler, L Benini IEEE Transactions on Parallel and Distributed Systems, 2023 | 7 | 2023 |
| Snitch: A 10 kGE pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads F Zaruba, F Schuiki, T Hoefler, L Benini arXiv preprint cs.AR/2002.10143, 2020 | 7 | 2020 |
| Ntx: An energyefficient streaming accelerator for floating-point generalized reduction workloads in 22 nm fd-soi. In 2019 Design, Automation & Test in Europe Conference … F Schuiki, M Schaffner, L Benini IEEE, 2019 | 4 | 2019 |
| Live demonstration: Exploiting body-biasing for static corner trimming and maximum energy efficiency operation in 22nm fdx technology A Di Mauro, F Zaruba, F Schuiki, S Mach, L Benini 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2020 | 3 | 2020 |
Luca BeniniETH Zürich, Università di BolognaVerified email at unibo.it
