Advances, challenges and opportunities in 3D CMOS sequential integration P Batude, M Vinet, B Previtali, C Tabone, C Xu, J Mazurier, O Weber, ... 2011 International Electron Devices Meeting, 7.3. 1-7.3. 4, 2011 | 418 | 2011 |
Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length P Batude, M Vinet, C Xu, B Previtali, C Tabone, C Le Royer, L Sanchez, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 158-159, 2011 | 275 | 2011 |
20nm gate length trigate pFETs on strained SGOI for high performance CMOS L Hutin, M Cassé, C Le Royer, JF Damlencourt, A Pouydebasque, C Xu, ... 2010 Symposium on VLSI Technology, 37-38, 2010 | 37 | 2010 |
Low temperature FDSOI devices, a key enabling technology for 3D sequential integration P Batude, B Sklenard, C Xu, B Previtali, B De Salvo, M Vinet 2013 International Symposium on VLSI Technology, Systems and Application …, 2013 | 18 | 2013 |
Replacement low-K spacer J Wan, JP Liu, G Bouche, A Wei, LH Vanamurthy, XU Cuiqin, ... US Patent 9,129,987, 2015 | 16 | 2015 |
Dopant diffusion barrier to form isolated source/drains in a semiconductor device J Wan, J Liu, C Gaire, M Hariharaputhiran, ACH Wei, BV Krishnan, ... US Patent App. 14/164,368, 2015 | 14 | 2015 |
Revisited approach for the characterization of Gate Induced Drain Leakage Q Rafhay, C Xu, P Batude, M Mouis, M Vinet, G Ghibaudo Solid-state electronics 71, 37-41, 2012 | 10 | 2012 |
FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650° C) B Sklenard, C Xu, P Batude, B Previtali, C Tabone, Q Rafhay, ... 2012 13th International Conference on Ultimate Integration on Silicon (ULIS …, 2012 | 9 | 2012 |
Threshold voltage tuning of 22 nm FD-SOI devices fabricated with metal gate last process C Xu, X Wang, W Liu 2019 International Conference on IC Design and Technology (ICICDT), 1-4, 2019 | 6 | 2019 |
Improvements in low temperature (< 625° C) FDSOI devices down to 30nm gate length C Xu, P Batude, M Vinet, M Mouis, M Casse, B Sklénard, B Colombeau, ... Proceedings of Technical Program of 2012 VLSI Technology, System and …, 2012 | 6 | 2012 |
Evaluation of Al-doped SPE ultrashallow P+ N junctions for use as PNP SiGe HBT emitters Y Civale, G Lorito, C Xu, LK Nanver, R Van Der Toorn Extended Abstracts-2008 8th International Workshop on Junction Technology …, 2008 | 6 | 2008 |
Stress memorization techniques for transistor devices JM Van Meer, XU Cuiqin, I Ferain US Patent 9,231,079, 2016 | 4 | 2016 |
Self-aligned contact openings over fins of a semiconductor device J Wan, X Hu, J Liu, GP Wells, ACH Wei, G Bouche, XU Cuiqin US Patent App. 14/258,279, 2015 | 4 | 2015 |
Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs B Sklenard, P Batude, Q Rafhay, I Martin-Bragado, C Xu, B Previtali, ... Solid-state electronics 88, 9-14, 2013 | 4 | 2013 |
Ion-Ioff performance analysis of FDSOI MOSFETs with low processing temperature C Xu, P Batude, C Rauer, C Le Royer, L Hutin, A Pouydebasque, ... Solid-State Devices Meeting, xx, 2010 | 4 | 2010 |
Preserving the seed layer on STI edge and improving the epitaxial growth J Wan, C Jer-Hueih James, XU Cuiqin, P Nagaiah US Patent 10,020,383, 2018 | 3 | 2018 |
FDSOI: A solution to suppress boron deactivation in low temperature processed devices C Xu, P Batude, B Sklenard, M Vinet, M Mouis, B Previtali, FY Liu, ... 2012 12th International Workshop on Junction Technology, 69-72, 2012 | 3 | 2012 |
Improved extraction of GIDL in FDSOI devices for proper junction quality analysis C Xu, P Batude, K Romanjek, C Le Royer, C Tabone, B Previtali, MA Jaud, ... 2011 Proceedings of the European Solid-State Device Research Conference …, 2011 | 3 | 2011 |
Stress memorization techniques for transistor devices M Sinha, P Kannan, XU Cuiqin, T Wang, SK Regonda US Patent 9,741,853, 2017 | 2 | 2017 |
Advanced 22nm FD-SOI Technolgy With Metal Gate Last Process XU Cuiqin, W Changfeng, L Duanquan 2019 IEEE International Conference on Electron Devices and Solid-State …, 2019 | 1 | 2019 |