Prati
Nitanshu Chauhan
Nitanshu Chauhan
National Institute of Technology Uttarakhand , Indian Institute of Technology Roorkee
Potvrđena adresa e-pošte na nituk.ac.in
Naslov
Citirano
Citirano
Godina
Impact of random spatial fluctuation in non-uniform crystalline phases on the device variation of ferroelectric FET
C Garg, N Chauhan, S Deng, AI Khan, S Dasgupta, A Bulusu, K Ni
IEEE Electron Device Letters 42 (8), 1160-1163, 2021
302021
A novel twofold tunnel FET with reduced miller capacitance: proposal and investigation
N Bagga, N Chauhan, D Gupta, S Dasgupta
IEEE Transactions on Electron Devices 66 (7), 3202-3208, 2019
202019
Negative-to-positive differential resistance transition in ferroelectric FET: physical insight and utilization in analog circuits
N Chauhan, N Bagga, S Banchhor, A Datta, S Dasgupta, A Bulusu
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 69 …, 2021
152021
BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective
N Chauhan, N Bagga, S Banchhor, C Garg, A Sharma, A Datta, ...
Nanotechnology 33 (8), 085203, 2021
132021
Performance optimization of analog circuits in negative capacitance transistor technology
O Prakash, N Chauhan, A Gupta, H Amrouch
Microelectronics Journal 115, 105193, 2021
132021
Demonstration of a novel tunnel FET with channel sandwiched by drain
N Bagga, N Chauhan, S Banchhor, D Gupta, S Dasgupta
Semiconductor Science and Technology 35 (1), 015008, 2019
132019
Investigation of trap-induced performance degradation and restriction on higher ferroelectric thickness in negative capacitance FDSOI FET
C Garg, N Chauhan, A Sharma, S Banchhor, A Doneria, S Dasgupta, ...
IEEE Transactions on Electron Devices 68 (10), 5298-5304, 2021
122021
Traps based reliability barrier on performance and revealing early ageing in negative capacitance FET
A Gupta, G Bajpai, P Singhal, N Bagga, O Prakash, S Banchhor, ...
2021 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2021
122021
Cleaved-gate ferroelectric FET for reliable multi-level cell storage
N Bagga, K Ni, N Chauhan, O Prakash, XS Hu, H Amrouch
2022 IEEE International Reliability Physics Symposium (IRPS), P5-1-P5-5, 2022
102022
Real time implementation of convolutional neural network to detect plant diseases using internet of things
G Bajpai, A Gupta, N Chauhan
VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019
102019
Physical cause and impact of negative capacitance effect in ferroelectric P (VDF-TrFE) gate stack and its application to landau transistor
KJ Singh, N Chauhan, A Bulusu, S Dasgupta
IEEE Open Journal of Ultrasonics, Ferroelectrics, and Frequency Control 2, 55-64, 2022
72022
Variability Effects in FinFET Transistors and Emerging NC-FinFET
A Gupta, N Chauhan, O Prakash, H Amrouch
2021 International Conference on IC Design and Technology (ICICDT), 1-4, 2021
62021
Impact of random spatial fluctuation in non-uniform crystalline phases on multidomain MFIM capacitor and negative capacitance FDSOI
N Chauhan, C Garg, K Ni, AK Behera, S Yadav, S Banchhor, N Bagga, ...
2022 IEEE International Reliability Physics Symposium (IRPS), P23-1-P23-6, 2022
52022
A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors
S Banchhor, N Chauhan, B Anand
Semiconductor Science and Technology 36 (3), 035005, 2021
42021
Gain stabilization methodology for FinFET amplifiers considering self-heating effect
S Banchhor, N Chauhan, A Doneria, B Anand
2021 34th International Conference on VLSI Design and 2021 20th …, 2021
32021
Demonstration of a novel ferroelectric-dielectric negative capacitance tunnel FET
N Bagga, N Chauhan, A Bulusu, S Dasgupta
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK …, 2019
32019
On the resiliency of nc-finfet srams against variation: Mfis structure
A Gupta, N Chauhan, O Prakash, H Amrouch
2021 International Conference on Simulation of Semiconductor Processes and …, 2021
22021
Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs
S Yadav, N Chauhan, R Chawla, A Sharma, S Banchhor, R Pratap, ...
Semiconductor Science and Technology 37 (8), 085023, 2022
12022
A physical insight into variation aware minimum V DD for deep subthreshold operation of FinFET
S Yadav, N Chauhan, S Tyagi, A Sharma, S Banchhor, R Joshi, R Pratap, ...
Semiconductor Science and Technology 36 (12), 125002, 2021
12021
Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification
N Chauhan, G Bajpai, S Banchhor, N Bagga
2020 24th International Symposium on VLSI Design and Test (VDAT), 1-5, 2020
12020
Sustav trenutno ne može provesti ovu radnju. Pokušajte ponovo kasnije.
Članci 1–20