Prati
Girish Pahwa
Girish Pahwa
Executive Director, Berkeley Device Modeling Center, UC Berkeley
Potvrđena adresa e-pošte na berkeley.edu
Naslov
Citirano
Citirano
Godina
Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance—Part II: Model validation
G Pahwa, T Dutta, A Agarwal, S Khandelwal, S Salahuddin, C Hu, ...
IEEE Transactions on Electron Devices 63 (12), 4986-4992, 2016
1842016
Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance-Part I: Model Description
G Pahwa, T Dutta, A Agarwal, S Khandelwal, S Salahuddin, C Hu, ...
IEEE Transactions on Electron Devices 63 (12), 4981 - 4985, 2016
1842016
Physical insights on negative capacitance transistors in nonhysteresis and hysteresis regimes: MFMIS versus MFIS structures
G Pahwa, T Dutta, A Agarwal, YS Chauhan
IEEE Transactions on Electron Devices 65 (3), 867-873, 2018
1142018
Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Subthreshold Behavior
G Pahwa, A Agarwal, YS Chauhan
IEEE Transactions on Electron Devices 65 (11), 5130 - 5136, 2018
1112018
Compact model for ferroelectric negative capacitance transistor with MFIS structure
G Pahwa, T Dutta, A Agarwal, YS Chauhan
IEEE Transactions on Electron Devices 64 (3), 1366-1374, 2017
962017
Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM
T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan
IEEE Electron Device Letters 38 (8), 1161-1164, 2017
812017
Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance
H Amrouch, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan
IEEE Access 6, 52754-52765, 2018
712018
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach
G Pahwa, T Dutta, A Agarwal, YS Chauhan
European Solid-State Circuits Conference, 49-54, 2016
672016
Compact modeling of drain current, charges, and capacitances in long-channel gate-all-around negative capacitance MFIS transistor
AD Gaidhane, G Pahwa, A Verma, YS Chauhan
IEEE Transactions on Electron Devices 65 (5), 2024-2032, 2018
542018
Impact of variability on processor performance in negative capacitance finfet technology
H Amrouch, G Pahwa, AD Gaidhane, CK Dabhi, F Klemme, O Prakash, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 3127-3137, 2020
462020
Impact of process variations on negative capacitance FinFET devices and circuits
T Dutta, G Pahwa, A Agarwal, YS Chauhan
IEEE Electron Device Letters 39 (1), 147-150, 2017
402017
Numerical investigation of short-channel effects in negative capacitance MFIS and MFMIS transistors: Above-threshold behavior
G Pahwa, A Agarwal, YS Chauhan
IEEE Transactions on Electron Devices 66 (3), 1591-1598, 2019
372019
Compact modeling of temperature effects in FDSOI and FinFET devices down to cryogenic temperatures
G Pahwa, P Kushwaha, A Dasgupta, S Salahuddin, C Hu
IEEE Transactions on Electron Devices 68 (9), 4223-4230, 2021
252021
Impact of interface traps on negative capacitance transistor: Device and circuit reliability
O Prakash, A Gupta, G Pahwa, J Henkel, YS Chauhan, H Amrouch
IEEE Journal of the Electron Devices Society 8, 1193-1201, 2020
242020
Unveiling the impact of IR-drop on performance gain in NCFET-based processors
H Amrouch, S Salamin, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan
IEEE Transactions on Electron Devices 66 (7), 3215-3223, 2019
232019
Performance, power and cooling trade-offs with NCFET-based many-cores
M Rapp, S Salamin, H Amrouch, G Pahwa, Y Chauhan, J Henkel
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
212019
Gate-induced drain leakage in negative capacitance FinFETs
AD Gaidhane, G Pahwa, A Verma, YS Chauhan
IEEE Transactions on Electron Devices 67 (3), 802-809, 2020
172020
NCFET-aware voltage scaling
S Salamin, M Rapp, H Amrouch, G Pahwa, Y Chauhan, J Henkel
2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019
162019
On the resiliency of NCFET circuits against voltage over-scaling
G Paim, G Zervakis, G Pahwa, YS Chauhan, EAC da Costa, S Bampi, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (4), 1481-1492, 2021
142021
Compact modeling of surface potential, drain current and terminal charges in negative capacitance nanosheet FET including quasi-ballistic transport
AD Gaidhane, G Pahwa, A Dasgupta, A Verma, YS Chauhan
IEEE Journal of the Electron Devices Society 8, 1168-1176, 2020
132020
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