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Bingfeng Mei
Bingfeng Mei
Principal Scientist at Broadcom
Verified email at broadcom.com
Title
Cited by
Cited by
Year
ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix
B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins
Field Programmable Logic and Application: 13th International Conference, FPL …, 2003
8162003
Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins
IEE Proceedings-Computers and Digital Techniques 150 (5), 255-261, 2003
3152003
DRESC: A retargetable compiler for coarse-grained reconfigurable architectures
B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins
2002 IEEE International Conference on Field-Programmable Technology, 2002 …, 2002
2832002
Architecture exploration for a reconfigurable architecture template
B Mei, A Lambrechts, JY Mignolet, D Verkest, R Lauwereins
IEEE Design & Test of Computers 22 (2), 90-101, 2005
2392005
Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: A case study
B Mei, S Vernalde, D Verkest, R Lauwereins
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
1942004
Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes
FJ Veredas, M Scheppler, W Moffat, B Mei
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
1332005
A hardware-software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems
B Mei, P Schaumont, S Vernalde
Proceedings of ProRISC, 405-411, 2000
1312000
A coarse-grained reconfigurable architecture template and its compilation techniques
B Mei
742005
Implementation of a coarse-grained reconfigurable media processor for AVC decoder
B Mei, B De Sutter, T Vander Aa, M Wouters, A Kanstein, S Dupont
Journal of signal processing systems 51, 225-243, 2008
722008
Mapping an H. 264/AVC decoder onto the ADRES reconfigurable architecture
B Mei, FJ Veredas, B Masschelein
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
662005
Design and optimization of dynamically reconfigurable embedded systems
B Mei, S Vernalde, H De Man, R Lauwereins
IMEC vzw, 2003
632003
Adres & dresc: Architecture and compiler for coarse-grain reconfigurable processors
B Mei, M Berekovic, JY Mignolet
Fine-and coarse-grain reconfigurable computing, 255-297, 2007
592007
Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays
B De Sutter, P Coene, T Vander Aa, B Mei
ACM Sigplan Notices 43 (7), 151-160, 2008
482008
Memory arrangement for multi-processor systems including a memory queue
B Mei, SJ Kim, O Allam
US Patent 8,560,795, 2013
392013
Interconnect exploration for energy versus performance tradeoffs for coarse grained reconfigurable architectures
A Lambrechts, P Raghavan, M Jayapala, B Mei, F Catthoor, D Verkest
IEEE transactions on very large scale integration (VLSI) systems 17 (1), 151-155, 2008
172008
Development of a design framework for platform-independent networked reconfiguration of software and hardware
Y Ha, B Mei, P Schaumont, S Vernalde, R Lauwereins, H De Man
Field-Programmable Logic and Applications: 11th International Conference …, 2001
162001
Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays
SJE Wilton, N Kafafi, B Mei, S Vernalde
Proceedings. 2004 IEEE International Conference on Field-Programmable …, 2004
152004
Design style case study for embedded multi media compute nodes
A Lambrechts, TV Aa, M Jayapala, G Talavera, A Leroy, A Shickova, ...
25th IEEE International Real-Time Systems Symposium, 104-113, 2004
132004
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
TV Aa, BF Mei, B De Sutter
Proceedings of the 2007 international conference on Compilers, architecture …, 2007
102007
Mapping of video compression algorithms on the ADRES coarse-Ggrain reconfigurable array
M Berekovic
102005
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