Gerhard Schrom
Gerhard Schrom
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A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS
J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 108-109, 2010
FIVR—Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs
EA Burton, G Schrom, F Paillet, J Douglas, WJ Lambert, K Radhakrishnan, ...
2014 IEEE Applied Power Electronics Conference and Exposition-APEC 2014, 432-439, 2014
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package
P Hazucha, G Schrom, J Hahn, BA Bloechel, P Hack, GE Dermer, ...
IEEE Journal of Solid-State Circuits 40 (4), 838-845, 2005
Review of on-chip inductor structures with magnetic films
DS Gardner, G Schrom, F Paillet, B Jamieson, T Karnik, S Borkar
IEEE Transactions on Magnetics 45 (10), 4760-4766, 2009
CMOS fabrication process utilizing special transistor orientation
M Armstrong, G Schrom, S Tyagi, PA Packan, KJ Kuhn, S Thompson
US Patent 7,312,485, 2007
A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control
G Schrom, P Hazucha, J Hahn, DS Gardner, BA Bloechel, G Dermer, ...
2004 IEEE 35th annual power electronics specialists conference (IEEE Cat. No …, 2004
Integrated on-chip inductors with magnetic films
DS Gardner, G Schrom, P Hazucha, F Paillet, T Karnik, S Borkar, ...
2006 International Electron Devices Meeting, 1-4, 2006
Indium-boron dual halo MOSFET
CE Weber, G Schrom, IR Post, MA Stettler
US Patent 7,226,843, 2007
Integrated on-chip inductors using magnetic material
DS Gardner, G Schrom, P Hazucha, F Paillet, T Karnik, S Borkar, ...
Journal of Applied Physics 103 (7), 07E927, 2008
A 100MHz eight-phase buck converter delivering 12A in 25mm2 using air-core inductors
G Schrom, P Hazucha, F Paillet, DJ Rennie, ST Moon, DS Gardner, ...
APEC 07-Twenty-Second Annual IEEE Applied Power Electronics Conference and …, 2007
Purge-based floating body memory
A Keshavarzi, SH Tang, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,230,846, 2007
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation
G Schrom, P Hazucha, JH Hahn, V Kursun, D Gardner, S Narendra, ...
Proceedings of the 2004 international symposium on Low power electronics and …, 2004
Determination of the line edge roughness specification for 34 nm devices
T Linton, M Chandhok, BJ Rice, G Schrom
Digest. International Electron Devices Meeting,, 303-306, 2002
High voltage tolerant linear regulator with fast digital control for biasing of integrated DC-DC converters
P Hazucha, ST Moon, G Schrom, F Paillet, D Gardner, S Rajapandian, ...
IEEE Journal of Solid-State Circuits 42 (1), 66-73, 2006
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
A Keshavarzi, G Schrom, S Tang, S Ma, K Bowman, S Tyagi, K Zhang, ...
Proceedings of the 2005 international symposium on Low power electronics and …, 2005
Integrated inductor
P Hazucha, E Burton, TT Nguyen, G Schrom, F Paillet, K Radhakrishnan, ...
US Patent 7,636,242, 2009
Ultra-low-power CMOS technology
G Schrom
na, 1998
Ultra-low-power CMOS technologies
G Schrom, S Selberherr
1996 International Semiconductor Conference. 19th Edition. CAS'96 …, 1996
Level shifter
G Schrom, D Somasekhar, P Hazucha, S Tang, V De
US Patent 7,199,617, 2007
MINIMOS-NT user’s guide
T Binder, K Dragosits, T Grasser, R Klima, M Knaipp, H Kosina, R Mlekus, ...
Institut für Mikroelektronik 85, 49-65, 1998
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