Keshab K. Parhi

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Tong ZhangRensselaer Polytechnic InstitutePotvrđena adresa e-pošte na ecse.rpi.edu
Sohini RoychowdhuryAccenture USA, Santa Clara University, University of WashingtonPotvrđena adresa e-pošte na uw.edu
Bo YuanRutgers UniversityPotvrđena adresa e-pošte na soe.rutgers.edu
Yingjie LaoClemson UniversityPotvrđena adresa e-pošte na clemson.edu
David G. MESSERSCHMITTEmeritus Professor, University of California at BerkeleyPotvrđena adresa e-pošte na berkeley.edu
Zhongfeng WangNanjing UniversityPotvrđena adresa e-pošte na nju.edu.cn
Marc RiedelAssociate Professor of Electrical and Computer Engineering, University of MinnesotaPotvrđena adresa e-pošte na umn.edu
Chris H. KimUniversity of MinnesotaPotvrđena adresa e-pošte na umn.edu
Naresh ShanbhagProfessor of Electrical and Computer Engineering, University of Illinois at Urbana-ChampaignPotvrđena adresa e-pošte na illinois.edu
Xinmiao ZhangThe Ohio State UniversityPotvrđena adresa e-pošte na case.edu
Manohar AyinalaPhD, University of MinnesotaPotvrđena adresa e-pošte na umn.edu
Theoden NetoffUniversity of MinnesotaPotvrđena adresa e-pošte na umn.edu
Yin LiuUniversity of Minnesota, Twin CitiesPotvrđena adresa e-pošte na umn.edu
Aaron CohenU.S. Naval Research LaboratoryPotvrđena adresa e-pošte na nrl.navy.mil
Kathryn Regan CullenUniversity of MinnesotaPotvrđena adresa e-pošte na umn.edu
Chen ZhouUniversity of MinnesotaPotvrđena adresa e-pošte na umn.edu
S V Sandeep AvvaruPhD Student, Univeristy of MinnesotaPotvrđena adresa e-pošte na umn.edu
Sandhya KoteshwaraIBM Research, University of MinnesotaPotvrđena adresa e-pošte na umn.edu
Hua JiangNetflix, Inc.Potvrđena adresa e-pošte na netflix.com
Bhaskar SenMicrosoft, University of MinnesotaPotvrđena adresa e-pošte na umn.edu

Prati

Keshab K. Parhi

University of Minnesota, Erwin A. Kelen Chair in Electrical Engineering

Potvrđena adresa e-pošte na umn.edu - Početna stranica

VLSI Signal Processing VLSI Machine Learning Neuroengineering DNA Computing


Naslov Poredaj po navodima Poredaj po godini Poredaj po naslovu	Citirano Citirano	Godina
VLSI digital signal processing systems: design and implementation KK Parhi John Wiley & Sons, 1999	2661*	1999
High-speed VLSI architectures for the AES algorithm X Zhang, KK Parhi IEEE transactions on very large scale integration (VLSI) systems 12 (9), 957-967, 2004	598	2004
VLSI architectures for discrete wavelet transforms KK Parhi, T Nishitani IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 (2), 191-202, 1993	550	1993
Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding KK Parhi, DG Messerschmitt IEEE Transactions on Computers 40 (2), 178-195, 1991	488	1991
Seizure prediction with spectral power of EEG using cost‐sensitive support vector machines Y Park, L Luo, KK Parhi, T Netoff Epilepsia 52 (10), 1761-1770, 2011	453	2011
Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition KK Parhi, DG Messerschmitt IEEE Transactions on Acoustics, Speech, and Signal Processing 37 (7), 1099-1117, 1989	453	1989
DREAM: diabetic retinopathy analysis using machine learning S Roychowdhury, DD Koozekanani, KK Parhi IEEE journal of biomedical and health informatics 18 (5), 1717-1728, 2013	387	2013
Blood vessel segmentation of fundus images by major vessel extraction and subimage classification S Roychowdhury, DD Koozekanani, KK Parhi IEEE journal of biomedical and health informatics 19 (3), 1118-1128, 2014	358	2014
Low-energy digit-serial/parallel finite field multipliers L Song, KK Parhi Journal of VLSI signal processing systems for signal, image and video …, 1998	323	1998
Distributed scheduling of broadcasts in a radio network R Ramaswami, KK Parhi IEEE INFOCOM'89, Proceedings of the Eighth Annual Joint Conference of the …, 1989	290	1989
Iterative vessel segmentation of fundus images S Roychowdhury, DD Koozekanani, KK Parhi IEEE Transactions on Biomedical Engineering 62 (7), 1738-1749, 2015	273	2015
Design of low-error fixed-width modified booth multiplier KJ Cho, KC Lee, JG Chung, KK Parhi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (5), 522-531, 2004	270	2004
Algorithm transformation techniques for concurrent processors KK Parhi Proceedings of the IEEE 77 (12), 1879-1895, 1989	265	1989
Synthesis of control circuits in folded pipelined DSP architectures KK Parhi, CY Wang, AP Brown IEEE Journal of Solid-State Circuits 27 (1), 29-43, 1992	238	1992
Small area parallel Chien search architectures for long BCH codes Y Chen, KK Parhi Ieee Transactions on Very Large Scale Integration (VLSI) Systems 12 (5), 545-549, 2004	223*	2004
Efficient semisystolic architectures for finite-field arithmetic SK Jain, L Song, KK Parhi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6 (1), 101-113, 1998	223	1998
A systematic approach for design of digit-serial signal processing architectures KK Parhi IEEE Transactions on Circuits and Systems 38 (4), 358-375, 1991	218	1991
Low-area/power parallel FIR digital filter implementations DA Parker, KK Parhi Journal of VLSI signal processing systems for signal, image and video …, 1997	216*	1997
Early stopping criteria for energy-efficient low-latency belief-propagation polar code decoders B Yuan, KK Parhi IEEE transactions on signal processing 62 (24), 6496-6506, 2014	213	2014
Overlapped message passing for quasi-cyclic low-density parity check codes Y Chen, KK Parhi IEEE Transactions on Circuits and Systems I: Regular Papers 51 (6), 1106-1113, 2004	207	2004

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