Víctor Viñals-Yúfera

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Pablo Ibáñez MarínUniversidad Zaragoza, I3A, Departamento de Informática e Ingeniería de SistemasPotvrđena adresa e-pošte na unizar.es
Teresa MonrealUniversitat Politecnica de CatalunyaPotvrđena adresa e-pošte na ac.upc.edu
Darío Suárez GraciaAssociate Professor at the Universidad de ZaragozaPotvrđena adresa e-pošte na unizar.es
Juan SegarraUniversidad de ZaragozaPotvrđena adresa e-pošte na unizar.es
Mateo ValeroProfessor and director of the Barcelona Supercomputing CenterPotvrđena adresa e-pošte na bsc.es
Jesus Alastruey-BenedéProfesor de la Universidad de ZaragozaPotvrđena adresa e-pošte na unizar.es
Antonio GonzalezProfessor, Universitat Politecnica de CatalunyaPotvrđena adresa e-pošte na ac.upc.edu
José Luis Briz VelascoProfesor de Informática (UZ)Potvrđena adresa e-pošte na unizar.es
Marta Ortín ObónUniversity of ZaragozaPotvrđena adresa e-pošte na unizar.es
Rubén Gran TejeroUniversidad de ZaragozaPotvrđena adresa e-pošte na unizar.es
Maria GarzaranResearch assistant professor, University of Illinois at Urbana-ChampaignPotvrđena adresa e-pošte na uiuc.edu
Enrique Torres MorenoPotvrđena adresa e-pošte na unizar.es
Jorge AlbericioNVIDIAPotvrđena adresa e-pošte na nvidia.com
Milos PrvulovicProfessor of Computer Science, Georgia TechPotvrđena adresa e-pošte na cc.gatech.edu
Josep TorrellasProfessor of Computer Science, University of Illinois Urbana-ChampaignPotvrđena adresa e-pošte na illinois.edu
Lawrence RauchwergerProfessor of Computer Science, University of Illinois at Urbana-ChampaignPotvrđena adresa e-pošte na illinois.edu
Luis M. RamosUniversidad de ZaragozaPotvrđena adresa e-pošte na unizar.es
Maria Villarroya-GaudóProfesora de Arquitectura y Tecnología de Computadores (U. De Zaragoza)Potvrđena adresa e-pošte na unizar.es
Davide BertozziUniversity of FerraraPotvrđena adresa e-pošte na unife.it
Luca RaminiHewlett Packard EnterprisePotvrđena adresa e-pošte na hpe.com

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Víctor Viñals-Yúfera

Universidad de Zaragoza

Potvrđena adresa e-pošte na unizar.es - Početna stranica

Computer architecture


Naslov Poredaj po navodima Poredaj po godini Poredaj po naslovu	Citirano Citirano	Godina
Delaying physical register allocation through virtual-physical registers T Monreal, A González, M Valero, J González, V Vinals MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999	126	1999
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors MJ Garzarán, M Prvulovic, JM Llabería, V Viñals, L Rauchwerger, ... ACM Transactions on Architecture and Code Optimization (TACO) 2 (3), 247-279, 2005	64	2005
The reuse cache: Downsizing the shared last-level cache J Albericio, P Ibáñez, V Viñals, JM Llabería Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013	63	2013
Hardware schemes for early register release T Monreal, V Viñals, A González, M Valero Proceedings International Conference on Parallel Processing, 5-13, 2002	59	2002
Store buffer design in first-level multibanked data caches EF Torres, P Ibánez, V Viñals, JM Llabería 32nd International Symposium on Computer Architecture (ISCA'05), 469-480, 2005	50	2005
Tradeoffs in buffering memory state for thread-level speculation in multiprocessors MJ Garzaran, M Prvulovic, JM Llaberia, V Vinals, L Rauchwerger, ... The Ninth International Symposium on High-Performance Computer Architecture …, 2003	47	2003
Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems LC Aparicio, J Segarra, C Rodríguez, V Viñals Journal of Systems Architecture 57 (7), 695-706, 2011	36	2011
Late allocation and early release of physical registers T Monreal, V Vinals, J González, A González, M Valero IEEE Transactions on Computers 53 (10), 1244-1259, 2004	32	2004
Dynamic register renaming through virtual-physical registers T Monreal, A González, M Valero, J González, V Viñals Journal of Instruction Level Parallelism 2, 4-16, 2000	28	2000
Exploiting reuse locality on inclusive shared last-level caches J Albericio, P Ibánez, V Viñals, JM Llabería ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-19, 2013	27	2013
Multi-level adaptive prefetching based on performance gradient tracking LM Ramos, JL Briz, PE Ibáñez, V Viñals Journal of Instruction-Level Parallelism 13, 1-14, 2011	27	2011
Contrasting laser power requirements of wavelength-routed optical NoC topologies subject to the floorplanning, placement, and routing constraints of a 3-D-stacked system M Ortín-Obón, M Tala, L Ramini, V Viñals-Yufera, D Bertozzi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (7 …, 2017	25	2017
LP-NUCA: Networks-in-cache for high-performance low-power embedded processors DS Gracia, G Dimitrakopoulos, TM Arnal, MGH Katevenis, VV Yúfera IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (8 …, 2011	24	2011
Combining prefetch with instruction cache locking in multitasking real-time systems LC Aparicio, J Segarra, C Rodriguez, V Vinals 2010 IEEE 16th International Conference on Embedded and Real-Time Computing …, 2010	22	2010
Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP A Navarro-Torres, J Alastruey-Benedé, P Ibáñez-Marín, V Viñals-Yúfera Plos one 14 (8), e0220135, 2019	20	2019
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors M Ortín-Obón, D Suárez-Gracia, M Villarroya-Gaudó, C Izu, ... Microprocessors and Microsystems 42, 24-36, 2016	17	2016
Avoiding the WCET overestimation on LRU instruction cache LC Aparicio, J Segarra, C Rodríguez, JL Villarroel, V Viñals 2008 14th IEEE International Conference on Embedded and Real-Time Computing …, 2008	17	2008
Capturing the sensitivity of optical network quality metrics to its network interface parameters M Ortín‐Obón, L Ramini, V Viñals, D Bertozzi Concurrency and Computation: Practice and Experience 26 (15), 2504-2517, 2014	16	2014
TDR-LAB 2.0 Improved TDR Software for soil water content and electrical conductivity measurements E Fatás, J Vicente, B Latorre, F Lera, V Viñals, MV López, N Blanco, ... Procedia Environmental Sciences 19, 474-483, 2013	15	2013
Using software logging to support multiversion buffering in thread-level speculation MJ Garzarán, M Prvulovic, V Viñals, JM Llabería, L Rauchwerger, ... 2003 12th International Conference on Parallel Architectures and Compilation …, 2003	15	2003

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