| On-line monitoring for temporal logic robustness A Dokhanchi, B Hoxha, G Fainekos International Conference on Runtime Verification, 231-246, 2014 | 149 | 2014 |
| Mining parametric temporal logic properties in model-based design for cyber-physical systems B Hoxha, A Dokhanchi, G Fainekos International Journal on Software Tools for Technology Transfer 20, 79-93, 2018 | 108 | 2018 |
| Encoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic M Hekmatnejad, S Yaghoubi, A Dokhanchi, HB Amor, A Shrivastava, ... Proceedings of the 17th ACM-IEEE International Conference on Formal Methods …, 2019 | 67 | 2019 |
| Evaluating perception systems for autonomous vehicles using quality temporal logic A Dokhanchi, HB Amor, JV Deshmukh, G Fainekos Runtime Verification: 18th International Conference, RV 2018, Limassol …, 2018 | 55 | 2018 |
| Requirements driven falsification with coverage metrics A Dokhanchi, A Zutshi, RT Sriniva, S Sankaranarayanan, G Fainekos 2015 International Conference on Embedded Software (EMSOFT), 31-40, 2015 | 46 | 2015 |
| Towards formal specification visualization for testing and monitoring of cyber-physical systems B Hoxha, H Bach, H Abbas, A Dokhanchi, Y Kobayashi, G Fainekos Int. Workshop on Design and Implementation of Formal Tools and Systems, 2014 | 46 | 2014 |
| Metric interval temporal logic specification elicitation and debugging A Dokhanchi, B Hoxha, G Fainekos 2015 ACM/IEEE International Conference on Formal Methods and Models for …, 2015 | 39 | 2015 |
| Formal requirement debugging for testing and verification of cyber-physical systems A Dokhanchi, B Hoxha, G Fainekos ACM Transactions on Embedded Computing Systems (TECS) 17 (2), 1-26, 2017 | 38 | 2017 |
| Specifying and evaluating quality metrics for vision-based perception systems A Balakrishnan, AG Puranic, X Qin, A Dokhanchi, JV Deshmukh, HB Amor, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 36 | 2019 |
| ARCH-COMP18 Category Report: Results on the Falsification Benchmarks. A Dokhanchi, S Yaghoubi, B Hoxha, G Fainekos, G Ernst, Z Zhang, ... ARCH@ ADHS, 104-109, 2018 | 26 | 2018 |
| Vacuity aware falsification for MTL request-response specifications A Dokhanchi, S Yaghoubi, B Hoxha, G Fainekos 2017 13th IEEE Conference on Automation Science and Engineering (CASE), 1332 …, 2017 | 21 | 2017 |
| An efficient algorithm for monitoring practical TPTL specifications A Dokhanchi, B Hoxha, CE Tuncali, G Fainekos 2016 ACM/IEEE International Conference on Formal Methods and Models for …, 2016 | 19 | 2016 |
| ARCH-COMP17 Category Report: Preliminary Results on the Falsification Benchmarks. A Dokhanchi, S Yaghoubi, B Hoxha, G Fainekos ARCH@ CPSWeek, 170-174, 2017 | 14 | 2017 |
| Feasibility study of using the RF interconnects in large FPGAs to improve routing tracks usage A Dokhanchi, A Jahanian, E Mehrshahi, MT Teimoori 2011 IEEE Computer Society Annual Symposium on VLSI, 1-6, 2011 | 4 | 2011 |
| From formal requirement analysis to testing and monitoring of cyber-physical systems A Dokhanchi Arizona State University, 2017 | 3 | 2017 |
| Systems and methods for evaluating perception systems for autonomous vehicles using quality temporal logic G Fainekos, HB Amor, A Dokhanchi, J Deshmukh US Patent 11,586,914, 2023 | 2 | 2023 |
| Querying parametric temporal logic properties in model based design B Hoxha, A Dokhanchi, G Fainekos arXiv preprint arXiv:1512.07956, 2015 | 2 | 2015 |
| MITL specification debugging for monitoring of cyber-physical systems A Dokhanchi, B Hoxha, G Fainekos Electronic Proceedings in Theoretical Computer Science, EPTCS 232, 10-13, 2016 | 1 | 2016 |
| Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects MT Teimoori, A Jahanian, A Dokhanchi IEICE transactions on electronics 95 (10), 1610-1619, 2012 | | 2012 |
| Performance Improvement of Physical Retiming with Shortcut Insertion A Dokhanchi, M Rezvani, A Jahanian, MS Zamani 2008 IEEE Computer Society Annual Symposium on VLSI, 215-220, 2008 | | 2008 |
