Ilia Polian

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Bernd BeckerProfessor of Computer Science, University of FreiburgVerified email at informatik.uni-freiburg.de
Matthias SauerAdvantest Europe GmbHVerified email at advantest.com
John P HayesProfessor of EECS, University of MichiganVerified email at umich.edu
Hans-Joachim WunderlichProfessor Emeritus of Computer Science, University of StuttgartVerified email at informatik.uni-stuttgart.de
Alexandru PalerAalto UniversityVerified email at aalto.fi
Sudhakar ReddyDepartment of ECE, University of IowaVerified email at engineering.uiowa.edu
Simon DevittResearch Director, Center for Quantum Software and Information, University of Technology SydneyVerified email at uts.edu.au
Sandip KunduUniversity of MassachusettsVerified email at ecs.umass.edu
Martin KreuzerUniversity of PassauVerified email at uni-passau.de
Mariane ComteLIRMM, Université de MontpellierVerified email at umontpellier.fr
Sybille HellebrandUniversity of Paderborn, GermanyVerified email at uni-paderborn.de
Philipp JovanovicUniversity College LondonVerified email at jovanovic.io
Osnat KerenFaculty of Engineering , Bar-Ilan UniversityVerified email at biu.ac.il
Reinhard WilhelmComputer Science, Saarland University, Saarland Informatics Campus (SIC)Verified email at cs.uni-saarland.de
Raghavan KumarIntel LabsVerified email at intel.com
Hideo Fujiwara 藤原秀雄Professor Emeritus, NAISTVerified email at fujiwaralab.net
Jan ReinekeProfessor of Computer Science, Saarland University, Saarland Informatics CampusVerified email at cs.uni-saarland.de
Irith PomeranzPurdue UniversityVerified email at ecn.purdue.edu
Zebo PengProfessor of Computer Systems, Linkoping UniversityVerified email at liu.se
Viacheslav IzosimovResearcher, The Royal Institute of Technology (KTH)Verified email at kth.se

Ilia Polian

University of Stuttgart

Verified email at polian.de - Homepage

Hardware security Emerging architectures Test and reliability


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A definition and classification of timing anomalies J Reineke, B Wachter, S Thesing, R Wilhelm, I Polian, J Eisinger, ... 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06), 2006	288	2006
A family of logical fault models for reversible circuits I Polian, T Fiehn, B Becker, JP Hayes 14th Asian Test Symposium (ATS'05), 422-427, 2005	154	2005
Testing for missing-gate faults in reversible circuits JP Hayes, I Polian, B Becker 13th Asian test symposium, 100-105, 2004	145	2004
X-masking during logic BIST and its impact on defect coverage Y Tang, HJ Wunderlich, H Vranken, F Hapke, M Wittke, P Engelke, ... 2004 International Conferce on Test, 442-451, 2004	134	2004
Simulating resistive-bridging and stuck-at faults P Engelke, I Polian, M Renovell, B Becker IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006	107	2006
Fault-tolerant, high-level quantum circuits: form, compilation and description A Paler, I Polian, K Nemoto, SJ Devitt Quantum Science and Technology 2 (2), 025003, 2017	102	2017
Parametric trojans for fault-injection attacks on cryptographic hardware R Kumar, P Jovanovic, W Burleson, I Polian 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, 18-28, 2014	93	2014
A fault attack on the LED block cipher P Jovanovic, M Kreuzer, I Polian Constructive Side-Channel Analysis and Secure Design: Third International …, 2012	87	2012
Adaptive voltage over-scaling for resilient applications PK Krause, I Polian 2011 Design, Automation & Test in Europe, 1-6, 2011	82	2011
An analysis framework for transient-error tolerance JP Hayes, I Polian, B Becker 25th IEEE VLSI Test Symposium (VTS'07), 249-255, 2007	78	2007
Analysis and optimization of fault-tolerant embedded systems with hardened processors V Izosimov, I Polian, P Pop, P Eles, Z Peng 2009 Design, Automation & Test in Europe Conference & Exhibition, 682-687, 2009	76	2009
Power droop testing I Polian, A Czutro, S Kundu, B Becker 2006 International Conference on Computer Design, 243-250, 2006	72	2006
Selective hardening: Toward cost-effective error tolerance I Polian, JP Hayes IEEE Design & Test of Computers 28 (3), 54-63, 2010	71	2010
A simulator of small-delay faults caused by resistive-open defects A Czutro, N Houarche, P Engelke, I Polian, M Comte, M Renovell, ... 2008 13th European Test Symposium, 113-118, 2008	68	2008
Benchmarking the performance of portfolio optimization with QAOA S Brandhofer, D Braun, V Dehn, G Hellstern, M Hüls, Y Ji, I Polian, ... Quantum Information Processing 22 (1), 25, 2022	66	2022
Small-delay-fault ATPG with waveform accuracy M Sauer, A Czutro, I Polian, B Becker Proceedings of the International Conference on Computer-Aided Design, 30-36, 2012	62	2012
Functional constraints vs. test compression in scan-based delay testing I Polian, H Fujiwara Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006	60	2006
Automatic test pattern generation for interconnect open defects S Spinner, I Polian, P Engelke, B Becker, M Keim, WT Cheng 26th IEEE VLSI test symposium (vts 2008), 181-186, 2008	58	2008
Resistive bridge fault model evolution from conventional to ultra deep submicron I Polian, P Engelke, B Becker, S Kundu, JM Galliere, M Renovell 23rd IEEE VLSI Test Symposium (VTS'05), 343-348, 2005	58	2005
Building a better random number generator for stochastic computing F Neugebauer, I Polian, JP Hayes 2017 Euromicro Conference on Digital System Design (DSD), 1-8, 2017	56	2017

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