| Technological exploration of RRAM crossbar array for matrix-vector multiplication L Xia, P Gu, B Li, T Tang, X Yin, W Huangfu, S Yu, Y Cao, Y Wang, ... Journal of Computer Science and Technology 31 (1), 3-19, 2016 | 264 | 2016 |
| DAPPLE: A pipelined data parallel approach for training large models S Fan, Y Rong, C Meng, Z Cao, S Wang, Z Zheng, C Wu, G Long, J Yang, ... Proceedings of the 26th ACM SIGPLAN Symposium on Principles and Practice of …, 2021 | 250 | 2021 |
| MNSIM: Simulation platform for memristor-based neuromorphic computing system L Xia, B Li, T Tang, P Gu, PY Chen, S Yu, Y Cao, Y Wang, Y Xie, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 244 | 2017 |
| Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect S Yu, PY Chen, Y Cao, L Xia, Y Wang, H Wu 2015 IEEE International Electron Devices Meeting (IEDM), 17.3. 1-17.3. 4, 2015 | 237 | 2015 |
| Binary convolutional neural network on RRAM T Tang, L Xia, B Li, Y Wang, H Yang 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 782-787, 2017 | 222 | 2017 |
| Fault-tolerant training with on-line fault detection for RRAM-based neural computing systems L Xia, M Liu, X Ning, K Chakrabarty, Y Wang Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 179 | 2017 |
| Stuck-at fault tolerance in RRAM computing systems L Xia, W Huangfu, T Tang, X Yin, K Chakrabarty, Y Xie, Y Wang, H Yang IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (1 …, 2017 | 169 | 2017 |
| Time: A training-in-memory architecture for memristor-based deep neural networks M Cheng, L Xia, Z Zhu, Y Cai, Y Xie, Y Wang, H Yang Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 146 | 2017 |
| Switched by input: Power efficient structure for RRAM-based convolutional neural network L Xia, T Tang, W Huangfu, M Cheng, X Yin, B Li, Y Wang, H Yang Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 125 | 2016 |
| A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory F Su, WH Chen, L Xia, CP Lo, T Tang, Z Wang, KH Hsu, M Cheng, JY Li, ... 2017 Symposium on VLSI Technology, T260-T261, 2017 | 111 | 2017 |
| A configurable multi-precision CNN computing framework based on single bit RRAM Z Zhu, H Sun, Y Lin, G Dai, L Xia, S Han, Y Wang, H Yang Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 106 | 2019 |
| Merging the interface: Power, area and accuracy co-optimization for rram crossbar-based mixed-signal computing system B Li, L Xia, P Gu, Y Wang, H Yang Proceedings of the 52nd annual design automation conference, 1-6, 2015 | 103 | 2015 |
| MNSIM 2.0: A behavior-level modeling tool for memristor-based neuromorphic computing systems Z Zhu, H Sun, K Qiu, L Xia, G Krishnan, G Dai, D Niu, X Chen, XS Hu, ... Proceedings of the 2020 on Great Lakes Symposium on VLSI, 83-88, 2020 | 84 | 2020 |
| TIME: A training-in-memory architecture for RRAM-based deep neural networks M Cheng, L Xia, Z Zhu, Y Cai, Y Xie, Y Wang, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 75 | 2018 |
| Low power convolutional neural networks on a chip Y Wang, L Xia, T Tang, B Li, S Yao, M Cheng, H Yang 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 129-132, 2016 | 72 | 2016 |
| Fault-tolerant training enabled by on-line fault detection for RRAM-based neural computing systems L Xia, M Liu, X Ning, K Chakrabarty, Y Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 59 | 2018 |
| Computation-oriented fault-tolerance schemes for RRAM computing systems W Huangfu, L Xia, M Cheng, X Yin, T Tang, B Li, K Chakrabarty, Y Xie, ... 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 794-799, 2017 | 59 | 2017 |
| Spiking neural network with rram: Can we use it for real-world application? T Tang, L Xia, B Li, R Luo, Y Chen, Y Wang, H Yang 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 860-865, 2015 | 58 | 2015 |
| Low bit-width convolutional neural network on RRAM Y Cai, T Tang, L Xia, B Li, Y Wang, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 57 | 2019 |
| Long live time: improving lifetime for training-in-memory engines by structured gradient sparsification Y Cai, Y Lin, L Xia, X Chen, S Han, Y Wang, H Yang Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 57 | 2018 |
Yu Wang (汪玉)Department of Electronic Engineering, Tsinghua University, ChinaPotvrđena adresa e-pošte na mail.tsinghua.edu.cn
