PARO: Synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications F Hannig, H Ruckdeschel, H Dutta, J Teich Reconfigurable Computing: Architectures, Tools and Applications: 4th …, 2008 | 85 | 2008 |
A design methodology for hardware acceleration of adaptive filter algorithms in image processing H Dutta, F Hannig, J Teich, B Heigl, H Hornegger IEEE 17th International Conference on Application-specific Systems …, 2006 | 34 | 2006 |
Regular mapping for coarse-grained reconfigurable architectures F Hannig, H Dutta, J Teich 2004 IEEE International Conference on Acoustics, Speech, and Signal …, 2004 | 33 | 2004 |
Mapping of regular nested loop programs to coarse-grained reconfigurable arrays-constraints and methodology F Hannig, H Dutta, J Teich 18th International Parallel and Distributed Processing Symposium, 2004 …, 2004 | 32 | 2004 |
Co-Design of Massively Parallel Embedded Processor Architectures. F Hannig, H Dutta, A Kupriyanov, J Teich, R Schaffer, S Siegel, R Merker, ... ReCoSoC, 27-34, 2005 | 31 | 2005 |
Hierarchical partitioning for piecewise linear algorithms H Dutta, F Hannig, J Teich International Symposium on Parallel Computing in Electrical Engineering …, 2006 | 29 | 2006 |
A holistic approach for tightly coupled reconfigurable parallel processors H Dutta, D Kissler, F Hannig, A Kupriyanov, J Teich, B Pottier Microprocessors and Microsystems 33 (1), 53-62, 2009 | 28 | 2009 |
Model-based synthesis and optimization of static multi-rate image processing algorithms J Keinert, H Dutta, F Hannig, C Haubelt, J Teich 2009 Design, Automation & Test in Europe Conference & Exhibition, 135-140, 2009 | 20 | 2009 |
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: Architectural parameters and methodology F Hannig, H Dutta, J Teich International Journal of Embedded Systems 2 (1-2), 114-127, 2006 | 20 | 2006 |
Efficient control generation for mapping nested loop programs onto processor arrays H Dutta, F Hannig, H Ruckdeschel, J Teich Journal of Systems Architecture 53 (5-6), 300-309, 2007 | 14 | 2007 |
Controller synthesis for mapping partitioned programs on array architectures H Dutta, F Hannig, J Teich Architecture of Computing Systems-ARCS 2006: 19th International Conference …, 2006 | 13 | 2006 |
An execution flow for dynamic concurrent systems: simulation of WSN on a Smalltalk/CUDA environment H Dutta, T Failler, N Melot, B Pottier, S Stinckwich Proceedings of the SIMPAR 2010 Workshops International Conference on …, 2010 | 12 | 2010 |
Automatic FIR filter generation for FPGAs H Ruckdeschel, H Dutta, F Hannig, J Teich Embedded Computer Systems: Architectures, Modeling, and Simulation: 5th …, 2005 | 11 | 2005 |
Parallelization approaches for hardware accelerators–loop unrolling versus loop partitioning F Hannig, H Dutta, J Teich International Conference on Architecture of Computing Systems, 16-27, 2009 | 9 | 2009 |
Efficient mapping of streaming applications for image processing on graphics cards R Membarth, H Dutta, F Hannig, J Teich Transactions on High-Performance Embedded Architectures and Compilers V, 1-20, 2019 | 8 | 2019 |
Mapping of nested loop programs onto massively parallel processor arrays with memory and I/O constraints H Dutta, F Hannig, J Teich, FM auf der Heide, B Monien Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in …, 2006 | 8 | 2006 |
Efficient mapping of multiresolution image filtering algorithms on graphics processors R Membarth, F Hannig, H Dutta, J Teich Embedded Computer Systems: Architectures, Modeling, and Simulation: 9th …, 2009 | 7 | 2009 |
An execution flow for dynamic concurrent systems: simulation of wsn on a smalltalk/cuda environment. DYROS H Dutta, T Failler, N Melot, B Pottier, S Stinckwich SIMPAR10, Darmstadt, 2010 | 6 | 2010 |
Modeling and synthesis of communication subsystems for loop accelerator pipelines H Dutta, F Hannig, M Schmid, J Keinert ASAP 2010-21st IEEE International Conference on Application-specific Systems …, 2010 | 6 | 2010 |
Impact of loop tiling on the controller logic of acceleration engines H Dutta, J Zhai, F Hannig, J Teich 2009 20th IEEE International Conference on Application-specific Systems …, 2009 | 6 | 2009 |