Prati
Shairfe M. SALAHUDDIN
Shairfe M. SALAHUDDIN
Potvrđena adresa e-pošte na imec.be
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Citirano
Citirano
Godina
A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability
SM Salahuddin, H Jiao, V Kursun
International symposium on quality electronic design (ISQED), 353-358, 2013
512013
Eight-FinFET fully differential SRAM cell with enhanced read and write voltage margins
SM Salahuddin, M Chan
IEEE Transactions on Electron Devices 62 (6), 2014-2021, 2015
302015
SRAM with buried power distribution to improve write margin and performance in advanced technology nodes
SM Salahuddin, KA Shaik, A Gupta, B Chava, M Gupta, P Weckx, ...
IEEE Electron Device Letters 40 (8), 1261-1264, 2019
202019
A frequency multiplier using three ambipolar graphene transistors
HMD Kabir, SM Salahuddin
Microelectronics journal 70, 12-15, 2017
202017
Buried power SRAM DTCO and system-level benchmarking in N3
S Salahuddin, M Perumkunnil, ED Litta, A Gupta, P Weckx, J Ryckaert, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
82020
Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap/underlap bitline access transistors for enhanced read data stability
SM Salahuddin, H Jiao, V Kursun
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2331-2334, 2013
82013
Finfet sram cells with asymmetrical bitline access transistors for enhanced read stability
SM Salahuddin, V Kursun, H Jiao
Transactions on Electrical and Electronic Materials 16 (6), 293-302, 2015
72015
Buried Bitline for sub-5nm SRAM Design
R Mathur, M Bhargava, S Salahuddin, P Schuddinck, J Ryckaert, ...
2020 IEEE International Electron Devices Meeting (IEDM), 20.2. 1-20.2. 4, 2020
62020
From design to system-technology optimization for CMOS
J Ryckaert, B Chehab, D Jang, G Mirabelli, SM Salahuddin, P Schuddinck, ...
2021 International Symposium on VLSI Technology, Systems and Applications …, 2021
52021
3D-optimized SRAM macro design and application to memory-on-logic 3D-IC at advanced nodes
R Chen, P Weckx, SM Salahuddin, SW Kim, G Sisto, G Van der Plas, ...
2020 IEEE International Electron Devices Meeting (IEDM), 15.2. 1-15.2. 4, 2020
52020
Improvement in data transmission efficiency in communication systems using scattering compensation techniques
S Raju, SM Salahuddin, MI Raza
Progress In Electromagnetics Research C 12, 237-251, 2010
52010
Buried Power Rail Metal exploration towards the 1 nm Node
A Gupta, D Radisic, JW Maes, OV Pedreira, JP Soulié, N Jourdan, ...
2021 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2021
42021
System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs
M Perumkunnil, F Yasin, S Rao, SM Salahuddin, D Milojevic, ...
2020 IEEE International Electron Devices Meeting (IEDM), 15.4. 1-15.4. 4, 2020
42020
Characterization of FinFET SRAM cells with asymmetrically gate underlapped bitline access transistors under process parameter fluctuations
SM Salahuddin, H Jiao, V Kursun
2013 IEEE International Conference of Electron Devices and Solid-state …, 2013
42013
DSSS IR UWB transceiver for intra/ inter chip wireless interconnect in future ULSI using reconfigurable monocycle pulse
S Raju, SM Salahuddin, MS Islam, PK Saha, AHMZ Alam
2008 International Conference on Computer and Communication Engineering, 2008
42008
Memory selector and memory device including same
SM Salahuddin, A Spessot
US Patent 11,374,058, 2022
32022
Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node
R Chen, G Sisto, A Jourdain, G Hiblot, M Stucchi, N Kakarla, B Chehab, ...
2021 IEEE International Electron Devices Meeting (IEDM), 22.4. 1-22.4. 4, 2021
32021
Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology
SM Salahuddin, ED Litta, A Gupta, R Ritzenthaler, M Schaekers, ...
IEEE Transactions on Electron Devices 67 (11), 4631-4635, 2020
32020
Buried Interconnects for Sub-5 nm SRAM Design
R Mathur, M Bhargava, B Cline, S Salahuddin, A Gupta, P Schuddinck, ...
IEEE Transactions on Electron Devices 69 (3), 1041-1047, 2022
22022
Write assist SRAM cell with asymmetrical bitline access transistors for enhanced data stability and write ability
SM Salahuddin, V Kursun
Journal of Circuits, Systems and Computers 25 (01), 1640009, 2016
22016
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