Prati
Hao Cai
Hao Cai
Southeast University, Nanjing, China
Potvrđena adresa e-pošte na telecom-paristech.fr
Naslov
Citirano
Citirano
Godina
A review of sparse recovery algorithms
EC Marques, N Maciel, L Naviner, H Cai, J Yang
IEEE access 7, 1300-1322, 2018
2222018
Compact model of dielectric breakdown in spin-transfer torque magnetic tunnel junction
Y Wang, H Cai, LA de Barros Naviner, Y Zhang, X Zhao, E Deng, JO Klein, ...
IEEE Transactions on Electron Devices 63 (4), 1762-1767, 2016
1402016
Robust ultra-low power non-volatile logic-in-memory circuits in FD-SOI technology
H Cai, Y Wang, LADB Naviner, W Zhao
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (4), 847-857, 2016
1002016
Magnetic tunnel junction applications
N Maciel, E Marques, L Naviner, Y Zhou, H Cai
Sensors 20 (1), 121, 2019
622019
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor
B Liu, H Cai, Z Wang, Y Sun, Z Shen, W Zhu, Y Li, Y Gong, W Ge, J Yang, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4733-4746, 2020
552020
High performance MRAM with spin-transfer-torque and voltage-controlled magnetic anisotropy effects
H Cai, W Kang, Y Wang, LADB Naviner, J Yang, W Zhao
Applied Sciences 7 (9), 929, 2017
542017
A 510-nW wake-up keyword-spotting chip using serial-FFT-based MFCC and binarized depthwise separable CNN in 28-nm CMOS
W Shan, M Yang, T Wang, Y Lu, H Cai, L Zhu, J Xu, C Wu, L Shi, J Yang
IEEE Journal of Solid-State Circuits 56 (1), 151-164, 2020
502020
A novel circuit design of true random number generator using magnetic tunnel junction
Y Wang, H Cai, LAB Naviner, JO Klein, J Yang, W Zhao
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016
442016
Compact thermal modeling of spin transfer torque magnetic tunnel junction
Y Wang, H Cai, LAB Naviner, Y Zhang, JO Klein, WS Zhao
Microelectronics Reliability 55 (9-10), 1649-1653, 2015
422015
Multiplexing sense-amplifier-based magnetic flip-flop in a 28-nm FDSOI technology
H Cai, Y Wang, W Zhao, LA de Barros Naviner
IEEE Transactions on Nanotechnology 14 (4), 761-767, 2015
402015
Proposal of analog in-memory computing with magnified tunnel magnetoresistance ratio and universal STT-MRAM cell
H Cai, Y Guo, B Liu, M Zhou, J Chen, X Liu, J Yang
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (4), 1519-1531, 2022
362022
Variation-resilient true random number generators based on multiple STT-MTJs
Y Qu, BF Cockburn, Z Huang, H Cai, Y Zhang, W Zhao, J Han
IEEE Transactions on Nanotechnology 17 (6), 1270-1281, 2018
342018
Stochastic computation with spin torque transfer magnetic tunnel junction
LA de Barros Naviner, H Cai, Y Wang, W Zhao, AB Dhia
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
332015
A self-timed voltage-mode sensing scheme with successive sensing and checking for STT-MRAM
Y Zhou, H Cai, L Xie, M Han, M Liu, S Xu, B Liu, W Zhao, J Yang
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (5), 1602-1614, 2020
322020
Reliability aware design of low power continuous-time sigma–delta modulator
H Cai, H Petit, JF Naviner
Microelectronics Reliability 51 (9-11), 1449-1453, 2011
262011
TG-SPP: A one-transmission-gate short-path padding for wide-voltage-range resilient circuits in 28-nm CMOS
W Shan, W Dai, C Zhang, H Cai, P Liu, J Yang, L Shi
IEEE Journal of Solid-State Circuits 55 (5), 1422-1436, 2019
252019
Precision adaptive MFCC based on R2SDF-FFT and approximate computing for low-power speech keywords recognition
B Liu, X Ding, H Cai, W Zhu, Z Wang, W Liu, J Yang
IEEE Circuits and Systems Magazine 21 (4), 24-39, 2021
232021
Exploring hybrid STT-MTJ/CMOS energy solution in near-/sub-threshold regime for IoT applications
H Cai, Y Wang, LA de Barros Naviner, J Yang, W Zhao
IEEE Transactions on magnetics 54 (2), 1-9, 2017
232017
A survey of in-spin transfer torque MRAM computing
H Cai, B Liu, J Chen, L Naviner, Y Zhou, Z Wang, J Yang
Science China Information Sciences 64 (6), 160402, 2021
222021
A hierarchical reliability simulation methodology for AMS integrated circuits and systems
H Cai, H Petit, JF Naviner
Journal of Low Power Electronics 8 (5), 697-705, 2012
202012
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