| An agile approach to building risc-v microprocessors Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ... IEEE Micro 36 (2), 8-20, 2016 | 167 | 2016 |
| A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ... IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016 | 87 | 2016 |
| Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors R Jevtic, HP Le, M Blagojevic, S Bailey, K Asanovic, E Alon, B Nikolic IEEE, 2014 | 72 | 2014 |
| A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ... VLSI Circuits (VLSI Circuits), 2015 Symposium on, C316-C317, 2015 | 55 | 2015 |
| Power measurement methodology for FPGA devices R Jevtic, C Carreras Instrumentation and Measurement, IEEE Transactions on 60 (1), 237-247, 2011 | 46 | 2011 |
| Power estimation of embedded multiplier blocks in FPGAs R Jevtic, C Carreras Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 18 (5 …, 2010 | 41 | 2010 |
| Technology variability from a design perspective B Nikolic, JH Park, J Kwak, B Giraud, Z Guo, LT Pang, SO Toh, R Jevtic, ... Circuits and Systems I: Regular Papers, IEEE Transactions on 58 (9), 1996-2009, 2011 | 28 | 2011 |
| Multiple-Input Relay Design for More Compact Implementation of Digital Logic Circuits J Jeon, L Hutin, R Jevtic, N Liu, Y Chen, R Nathanael, W Kwon, ... Electron Device Letters, IEEE 33 (2), 281-283, 2012 | 27 | 2012 |
| Fully integrated DC-DC converter and a 0.4 V 32-bit CPU with timing-error prevention supplied from a prototype 1.55 V Li-ion battery M Turnquist, M Hiienkari, J Makipaa, R Jevtic, E Pohjalainen, T Kallio, ... VLSI Circuits (VLSI Circuits), 2015 Symposium on, C320-C321, 2015 | 26 | 2015 |
| Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking Y Lee, B Zimmer, A Waterman, A Puggelli, J Kwak, R Jevtic, B Keller, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-45, 2015 | 24 | 2015 |
| A Low-Latency, Low-Power FPGA Implementation of ECG Signal Characterization Using Hermite Polynomials MP Desai, G Caffarena, R Jevtic, DG Márquez, A Otero Electronics 10 (19), 2324, 2021 | 21 | 2021 |
| Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models R Jevtic, C Carreras, G Caffarena International Journal of Electronics 95 (7), 653-668, 2008 | 21 | 2008 |
| Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits B Jovanovic, R Jevtic, C Carreras Industrial Informatics, IEEE Transactions on 10 (1), 393-398, 2014 | 20 | 2014 |
| A complete dynamic power estimation model for data-paths in FPGA DSP designs R Jevtic, C Carreras Integration, the VLSI Journal 45 (2), 172-185, 2012 | 20 | 2012 |
| EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation R Jevtic, M Ylitolva, C Calonge, M Ojanen, T Santti, L Koskinen IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021 | 14 | 2021 |
| Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes P Barrio, C Carreras, JA López, Ó Robles, R Jevtic, R Sierra Journal of Systems Architecture 60 (7), 579-591, 2014 | 12 | 2014 |
| Power estimation of dividers implemented in FPGAs R Jevtic, B Jovanovic, C Carreras Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011 | 11 | 2011 |
| Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices R Jevtic, M Ylitolva, L Koskinen 2018 28th International Symposium on Power and Timing Modeling, Optimization …, 2018 | 8 | 2018 |
| Switching activity models for power estimation in FPGA multipliers R Jevtic, C Carreras, G Caffarena Reconfigurable Computing: Architectures, Tools and Applications, 201-213, 2007 | 8 | 2007 |
| Analytical high-level power model for LUT-based components R Jevtic, C Carreras Integrated Circuit and System Design. Power and Timing Modeling …, 2009 | 7 | 2009 |
