| Ferroelectric HfO2 Memory Transistors With High-κ Interfacial Layer and Write Endurance Exceeding 1010 Cycles AJ Tan, YH Liao, LC Wang, N Shanker, JH Bae, C Hu, S Salahuddin IEEE Electron Device Letters 42 (7), 994-997, 2021 | 134 | 2021 |
| Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors SS Cheema, N Shanker, LC Wang, CH Hsu, SL Hsu, YH Liao, ... Nature 604 (7904), 65-71, 2022 | 132 | 2022 |
| Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO2 Oxide D Kwon, S Cheema, N Shanker, K Chatterjee, YH Liao, AJ Tan, C Hu, ... IEEE Electron Device Letters 40 (6), 993-996, 2019 | 123 | 2019 |
| Proposal for capacitance matching in negative capacitance field-effect transistors H Agarwal, P Kushwaha, YK Lin, MY Kao, YH Liao, A Dasgupta, ... IEEE Electron Device Letters 40 (3), 463-466, 2019 | 79 | 2019 |
| Experimental Demonstration of a Ferroelectric HfO2-Based Content Addressable Memory Cell AJ Tan, K Chatterjee, J Zhou, D Kwon, YH Liao, S Cheema, C Hu, ... IEEE Electron Device Letters 41 (2), 240-243, 2019 | 56 | 2019 |
| Negative capacitance, n-channel, Si FinFETs: Bi-directional sub-60 mV/dec, negative DIBL, negative differential resistance and improved short channel effect H Zhou, D Kwon, AB Sachid, Y Liao, K Chatterjee, AJ Tan, AK Yadav, ... 2018 IEEE Symposium on VLSI Technology, 53-54, 2018 | 52 | 2018 |
| Analysis and modeling of inner fringing field effect on negative capacitance FinFETs YK Lin, H Agarwal, P Kushwaha, MY Kao, YH Liao, K Chatterjee, ... IEEE Transactions on Electron Devices 66 (4), 2023-2027, 2019 | 45 | 2019 |
| Near threshold capacitance matching in a negative capacitance FET with 1 nm effective oxide thickness gate stack D Kwon, S Cheema, YK Lin, YH Liao, K Chatterjee, AJ Tan, C Hu, ... IEEE Electron Device Letters 41 (1), 179-182, 2019 | 43 | 2019 |
| Hot electrons as the dominant source of degradation for sub-5nm HZO FeFETs AJ Tan, M Pešić, L Larcher, YH Liao, LC Wang, JH Bae, C Hu, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 41 | 2020 |
| NCFET design considering maximum interface electric field H Agarwal, P Kushwaha, YK Lin, MY Kao, YH Liao, JP Duarte, ... IEEE Electron Device Letters 39 (8), 1254-1257, 2018 | 41 | 2018 |
| Response speed of negative capacitance FinFETs D Kwon, YH Liao, YK Lin, JP Duarte, K Chatterjee, AJ Tan, AK Yadav, ... 2018 IEEE Symposium on VLSI Technology, 49-50, 2018 | 41 | 2018 |
| Spacer engineering in negative capacitance FinFETs YK Lin, H Agarwal, MY Kao, J Zhou, YH Liao, A Dasgupta, P Kushwaha, ... IEEE Electron Device Letters 40 (6), 1009-1012, 2019 | 39 | 2019 |
| Variation caused by spatial distribution of dielectric and ferroelectric grains in a negative capacitance field-effect transistor MY Kao, AB Sachid, YK Lin, YH Liao, H Agarwal, P Kushwaha, JP Duarte, ... IEEE Transactions on Electron Devices 65 (10), 4652-4658, 2018 | 39 | 2018 |
| Anomalously beneficial gate-length scaling trend of negative capacitance transistors YH Liao, D Kwon, YK Lin, AJ Tan, C Hu, S Salahuddin IEEE Electron Device Letters 40 (11), 1860-1863, 2019 | 28 | 2019 |
| Fast read-after-write and depolarization fields in high endurance n-type ferroelectric FETs M Hoffmann, AJ Tan, N Shanker, YH Liao, LC Wang, JH Bae, C Hu, ... IEEE Electron Device Letters 43 (5), 717-720, 2022 | 26 | 2022 |
| Optimization of NCFET by matching dielectric and ferroelectric nonuniformly along the channel MY Kao, YK Lin, H Agarwal, YH Liao, P Kushwaha, A Dasgupta, ... IEEE Electron Device Letters 40 (5), 822-825, 2019 | 22 | 2019 |
| Effect of polycrystallinity and presence of dielectric phases on NC-FinFET variability YK Lin, MY Kao, H Agarwal, YH Liao, P Kushwaha, K Chatterjee, ... 2018 IEEE International Electron Devices Meeting (IEDM), 9.4. 1-9.4. 4, 2018 | 18 | 2018 |
| Electric field-induced permittivity enhancement in negative-capacitance FET YH Liao, D Kwon, S Cheema, N Shanker, AJ Tan, MY Kao, LC Wang, ... IEEE Transactions on Electron Devices 68 (3), 1346-1351, 2021 | 13 | 2021 |
| Negative-capacitance FinFETs: Numerical simulation, compact modeling and circuit evaluation JP Duarte, YK Lin, YH Liao, A Sachid, MY Kao, H Agarwal, P Kushwaha, ... 2018 International conference on simulation of semiconductor processes and …, 2018 | 13 | 2018 |
| Modeling and simulation of negative capacitance gate on Ge FETs YH Liao, ST Fan, CW Liu ECS Transactions 75 (8), 461, 2016 | 8 | 2016 |
