Yogesh S. Chauhan

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	Sve	Od 2018.
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i10-indeks	133	111

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Suautori

sourabh khandelwalUC BerkeleyPotvrđena adresa e-pošte na berkeley.edu
chenming huUniversity of California, BerkeleyPotvrđena adresa e-pošte na eecs.berkeley.edu
Amit AgarwalProfessor, Indian Institute of Technology, Kanpur (India)Potvrđena adresa e-pošte na iitk.ac.in
Girish PahwaExecutive Director, Berkeley Device Modeling Center, UC BerkeleyPotvrđena adresa e-pošte na berkeley.edu
Pragya KushwahaSpace Application Centre ISRO, Ahmedabad, IndiaPotvrđena adresa e-pošte na ieee.org
Juan Pablo Duarte SepulvedaApplePotvrđena adresa e-pošte na apple.com
Avirup DasguptaIndian Institute of Technology RoorkeePotvrđena adresa e-pošte na ece.iitr.ac.in
Ali M NIKNEJADUC BerkeleyPotvrđena adresa e-pošte na berkeley.edu
Hussam AmrouchProfessor (W3), Technical University of Munich (TUM)Potvrđena adresa e-pošte na tum.de
Sriramkumar VenugopalanSemiconductors ProfessionalPotvrđena adresa e-pošte na eecs.berkeley.edu
Sudip GhoshDST Young Scientist, IIT-KanpurPotvrđena adresa e-pošte na iitk.ac.in
Somnath bhowmickInian Institute of Technology, KanpurPotvrđena adresa e-pošte na iitk.ac.in
A.M. IonescuProfessor of NanoelectronicsPotvrđena adresa e-pošte na epfl.ch
chandan yadavAssistant Professor, National Institute of Technology Calicut, Kerala, IndiaPotvrđena adresa e-pošte na nitc.ac.in
Priyank RastogiIntel Technologies India Pvt. Ltd.Potvrđena adresa e-pošte na intel.com
Navid PaydavosiDevice Engineer, IntelPotvrđena adresa e-pošte na intel.com
Tapas DuttaUniversity of GlasgowPotvrđena adresa e-pošte na glasgow.ac.uk
Chetan Kumar DabhiUC Berkeley | BSIM Group | IIT Kanpur | NIT SuratPotvrđena adresa e-pošte na berkeley.edu
Amol GaidhanePostdoctoral Researcher, Arizona State University || Ph.D., IIT KanpurPotvrđena adresa e-pošte na asu.edu
Jörg HenkelProfessor of Computer Science, Karlsruhe Institute of TechnologyPotvrđena adresa e-pošte na kit.edu

Prati

Yogesh S. Chauhan

Fellow IEEE, FNAE, Professor-IIT Kanpur

Potvrđena adresa e-pošte na iitk.ac.in - Početna stranica

ASM GaN HEMT Compact Model BSIM SPICE Model Cryogenic Transistor Modeling Ferroelectric Negative Capacitance Transistor


Naslov Poredaj po navodima Poredaj po godini Poredaj po naslovu	Citirano Citirano	Godina
FinFET modeling for IC simulation and design: using the BSIM-CMG standard YS Chauhan, DD Lu, S Venugopalan, S Khandelwal, JP Duarte, ... Academic Press, 2015	199	2015
Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance—Part II: Model validation G Pahwa, T Dutta, A Agarwal, S Khandelwal, S Salahuddin, C Hu, ... IEEE Transactions on Electron Devices 63 (12), 4986-4992, 2016	184	2016
Analytical modeling of surface-potential and intrinsic charges in AlGaN/GaN HEMT devices S Khandelwal, YS Chauhan, TA Fjeldly IEEE Transactions on Electron Devices 59 (10), 2856-2860, 2012	158	2012
BSIM—SPICE models enable FinFET and UTB IC designs N Paydavosi, S Venugopalan, YS Chauhan, JP Duarte, S Jandhyala, ... IEEE Access 1, 201-215, 2013	128	2013
BSIM6: Analog and RF compact model for bulk MOSFET YS Chauhan, S Venugopalan, MA Chalkiadaki, MAU Karim, H Agarwal, ... IEEE Transactions on Electron Devices 61 (2), 234-244, 2013	117	2013
Physical insights on negative capacitance transistors in nonhysteresis and hysteresis regimes: MFMIS versus MFIS structures G Pahwa, T Dutta, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 65 (3), 867-873, 2018	114	2018
Robust surface-potential-based compact model for GaN HEMT IC design S Khandelwal, C Yadav, S Agnihotri, YS Chauhan, A Curutchet, T Zimmer, ... IEEE Transactions on Electron Devices 60 (10), 3216-3222, 2013	114	2013
Numerical investigation of short-channel effects in negative capacitance MFIS and MFMIS transistors: Subthreshold behavior G Pahwa, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 65 (11), 5130-5136, 2018	111	2018
Doping Strategies for Monolayer MoS₂ via Surface Adsorption: A Systematic Study P Rastogi, S Kumar, S Bhowmick, A Agarwal, YS Chauhan The Journal of Physical Chemistry C 118 (51), 30309-30314, 2014	106	2014
Analytical modeling of the suspended-gate FET and design insights for low-power logic K Akarvardar, C Eggimann, D Tsamados, YS Chauhan, GC Wan, ... IEEE transactions on Electron Devices 55 (1), 48-59, 2007	105	2007
BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control S Khandelwal, YS Chauhan, DD Lu, S Venugopalan, MAU Karim, ... IEEE Transactions on Electron Devices 59 (8), 2019-2026, 2012	100	2012
Compact model for ferroelectric negative capacitance transistor with MFIS structure G Pahwa, T Dutta, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 64 (3), 1366-1374, 2017	96	2017
ASM GaN: Industry standard model for GaN RF and power devices—Part 1: DC, CV, and RF model S Khandelwal, YS Chauhan, TA Fjeldly, S Ghosh, A Pampori, D Mahajan, ... IEEE Transactions on Electron Devices 66 (1), 80-86, 2018	87	2018
Capacitance modeling in dual field-plate power GaN HEMT for accurate switching behavior SA Ahsan, S Ghosh, K Sharma, A Dasgupta, S Khandelwal, YS Chauhan IEEE Transactions on Electron Devices 63 (2), 565-572, 2015	84	2015
Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan IEEE Electron Device Letters 38 (8), 1161-1164, 2017	81	2017
BSIM—Industry standard compact MOSFET models YS Chauhan, S Venugopalan, MA Karim, S Khandelwal, N Paydavosi, ... 2012 Proceedings of the European Solid-State Device Research Conference …, 2012	77	2012
Thickness and electric-field-dependent polarizability and dielectric constant in phosphorene P Kumar, BS Bhadoria, S Kumar, S Bhowmick, YS Chauhan, A Agarwal Physical Review B 93 (19), 195428, 2016	75	2016
RF SOI switch FET design and modeling tradeoffs for GSM applications S Parthasarathy, A Trivedi, S Sirohi, R Groves, M Olsen, YS Chauhan, ... 2010 23rd International Conference on VLSI Design, 194-199, 2010	75	2010
Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance H Amrouch, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan IEEE Access 6, 52754-52765, 2018	71	2018
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X I_ONusing compact modeling approach G Pahwa, T Dutta, A Agarwal, YS Chauhan ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 49-54, 2016	67	2016

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