| Delaying physical register allocation through virtual-physical registers T Monreal, A González, M Valero, J González, V Vinals MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999 | 126 | 1999 |
| Hardware schemes for early register release T Monreal, V Viñals, A González, M Valero Proceedings International Conference on Parallel Processing, 5-13, 2002 | 59 | 2002 |
| Late allocation and early release of physical registers T Monreal, V Vinals, J González, A González, M Valero IEEE Transactions on Computers 53 (10), 1244-1259, 2004 | 32 | 2004 |
| Virtual registers A Gonzalez, M Valero, J Gonzalez, T Monreal Proceedings Fourth International Conference on High-Performance Computing …, 1997 | 32 | 1997 |
| Concertina: Squeezing in cache content to operate at near-threshold voltage A Ferreron, D Suarez-Gracia, J Alastruey-Benede, T Monreal-Arnal, ... IEEE Transactions on Computers 65 (3), 755-769, 2015 | 28 | 2015 |
| Dynamic register renaming through virtual-physical registers T Monreal, A González, M Valero, J González, V Viñals Journal of Instruction Level Parallelism 2, 4-16, 2000 | 28 | 2000 |
| LP-NUCA: Networks-in-Cache for high-performance low-power embedded processors DS Gracia, G Dimitrakopoulos, TM Arnal, MGH Katevenis, VV Yúfera Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 20 (8 …, 2012 | 24 | 2012 |
| Light NUCA: a proposal for bridging the inter-cache latency gap D Suárez, T Monreal Arnal, F Vallejo, JR Beivide Palacio, V Viñals Yufera Design, Automation and Test in Europe 2009, 530-535, 2009 | 11 | 2009 |
| Microarchitectural support for speculative register renaming J Alastruey, T Monreal, V Viñals, M Valero 2007 IEEE International Parallel and Distributed Processing Symposium, 1-10, 2007 | 9 | 2007 |
| Selection of the register file size and the resource allocation policy on SMT processors J Alastruey, T Monreal, F Cazorla, V Viñals, M Valero 2008 20th International Symposium on Computer Architecture and High …, 2008 | 8 | 2008 |
| A Comparison of Cache Hierarchies for SMT Processors DS Gracia, TM Arnal, VV Yúfera Proc. of the 22th Jornadas de Paralelismo (JJPAR’11), 2011 | 6* | 2011 |
| Block disabling characterization and improvements in CMPs operating at ultra-low voltages A Ferrerón, D Suarez-Gracia, J Alastruey-Benedé, T Monreal, V Vinals 2014 IEEE 26th International Symposium on Computer Architecture and High …, 2014 | 5 | 2014 |
| Reuse detector: Improving the management of STT-RAM SLLCs R Rodríguez-Rodríguez, J Díaz, F Castro, P Ibáñez, D Chaver, V Viñals, ... The Computer Journal 61 (6), 856-880, 2018 | 4 | 2018 |
| Speculative early register release J Alastruey, T Monreal, V Viñals, M Valero Proceedings of the 3rd conference on Computing frontiers, 291-302, 2006 | 4 | 2006 |
| ReD: A reuse detector for content selection in exclusive shared last-level caches J Díaz, T Monreal, P Ibáñez, JM Llabería, V Viñals Journal of Parallel and Distributed Computing 125, 106-120, 2019 | 3 | 2019 |
| Selección de contenidos basada en reuso para caches compartidas en exclusión J Díaz Maag, T Monreal Arnal, V Viñals Yúfera, PE Ibáñez Marín, ... XXVI edición de las Jornadas de Paralelismo (JP2015): 23, 24 y 25 de …, 2015 | 2 | 2015 |
| An adaptive controller to save dynamic energy in lp-nuca DS Gracia, TM Arnal, VV Yúfera Proc. of the 22th Jornadas de Paralelismo (JJPAR’11), 2011 | 2 | 2011 |
| L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime C Escuin, P Ibáñez, D Navarro, T Monreal, JM Llabería, V Viñals Plos one 18 (2), e0278346, 2023 | 1 | 2023 |
| HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches C Escuin, AA Khan, P Ibañez, T Monreal, V Viñals, J Castrillon System Engineering for constrained embedded systems, 53-58, 2022 | 1 | 2022 |
| Near-optimal replacement policies for shared caches in multicore processors J Díaz, P Ibáñez, T Monreal, V Viñals, JM Llabería The Journal of Supercomputing 77, 11756-11785, 2021 | 1 | 2021 |
