Hamid R. Zarandi

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Dhiraj K PradhanProfessor of Computer Science, University of BristolVerified email at cs.bris.ac.uk
Hossein PedramAssociate professor of computer engineering at Amirkabir University of TechnologyVerified email at aut.ac.ir
Mohammad MaghsoudlooAssistant Professor, Department of Computer Engineering, Golestan UniversityVerified email at gu.ac.ir
Costas ArgyridesAdvanced Micro Devices (AMD), IncVerified email at costas.cy
Alireza EjlaliAssociate Professor, Department of Computer Engineering, Sharif University of TechnologyVerified email at sharif.edu
Amir M. HajisadeghiAmirkabir University of Technology (Tehran Polytechnic)Verified email at aut.ac.ir
Pooria M. YaghiniPhD, University of California, IrvineVerified email at uci.edu
Ashkan EghbalPhD. University of California IrvineVerified email at uci.edu
Alireza TajaryShahrood University of TechnologyVerified email at shahroodut.ac.ir
Mohsen RajiAssociate Professor, School of Electrical & Computer Engineering, Shiraz UniversityVerified email at shirazu.ac.ir
Athena AbdiAssistant Professor, Faculty of Computer Engineering, K. N. Toosi University of TechnologyVerified email at kntu.ac.ir
Hossein AsadiProfessor, Department of Computer Engineering, Sharif University of TechnologyVerified email at sharif.edu
Hamid Sarbazi-AzadProfessor of Computer Science and Engineering, Sharif University of Technology & IPMVerified email at sharif.edu
Javad Talafy DaryaniAmirkabir University of TechnologyVerified email at aut.ac.ir
Farzane ZokaeeSystem on Chip ArchitectureVerified email at amperecomputing.com
Jimson MathewIIT patnaVerified email at iitp.ac.in
Elham CheshmikhaniShahid Beheshti UniversityVerified email at sbu.ac.ir
Mohammad Hadi MottaghiPh.D, Amirkabir University of TechnologyVerified email at aut.ac.ir
Roghayeh MojaradPh.D.Verified email at u-pec.fr
Mahroo ZandrahimiDelft University of TechnologyVerified email at tudelft.nl

Hamid R. Zarandi

Associate Professor, Department of Computer Engineering, Amirkabir University of Technology

Verified email at aut.ac.ir - Homepage

Networks-on-Chip Reliable System Design Computer Architectures Embedded Systems


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Dependability analysis using a fault injection tool based on synthesizability of HDL models HR Zarandi, SG Miremadi, A Ejlali Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003	99	2003
Matrix codes: Multiple bit upsets tolerant method for SRAM memories C Argyrides, HR Zarandi, DK Pradhan 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007	60	2007
A fast and accurate fault tree analysis based on stochastic logic implemented on field-programmable gate arrays H Aliee, HR Zarandi IEEE Transactions on Reliability 62 (1), 13-22, 2012	58	2012
A hybrid fault injection approach based on simulation and emulation co-operation A Ejlali, SG Miremadi, H Zarandi, G Asadi, SB Sarmadi 2003 International Conference on Dependable Systems and Networks, 2003 …, 2003	54	2003
DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors MH Mottaghi, HR Zarandi Microprocessors and Microsystems 38 (1), 88-97, 2014	50	2014
Aligner: A process-in-memory architecture for short read alignment in rerams F Zokaee, HR Zarandi, L Jiang IEEE Computer Architecture Letters 17 (2), 237-240, 2018	48	2018
HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors M Kishani, HR Zarandi, H Pedram, A Tajary, M Raji, B Ghavami Design Automation for Embedded Systems 15, 289-310, 2011	39	2011
Fault injection into verilog models for dependability evaluation of digital systems HR Zarandi, SG Miremadi, A Ejlali Parallel and Distributed Computing, International Symposium on, 281-281, 2003	39	2003
Fault injection into SRAM-based FPGAs for the analysis of SEU effects G Asadi, SG Miremadi, HR Zarandi, A Ejlali Proceedings. 2003 IEEE International Conference on Field-Programmable …, 2003	38	2003
Fast SEU detection and correction in LUT configuration bits of SRAM-based FPGAs HR Zarandi, SG Miremadi, C Argyrides, DK Pradhan 2007 IEEE International Parallel and Distributed Processing Symposium, 1-6, 2007	34	2007
A fault‐tolerant core mapping technique in networks‐on‐chip F Khalili, HR Zarandi IET Computers & Digital Techniques 7 (6), 238-245, 2013	33	2013
A fault-tolerant low-energy multi-application mapping onto NoC-based multiprocessors F Khalili, HR Zarandi 2012 IEEE 15th International Conference on Computational Science and …, 2012	33	2012
Two efficient software techniques to detect and correct control-flow errors HR Zarandi, M Maghsoudloo, N Khoshavi 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing …, 2010	33	2010
Fault tree analysis using stochastic logic: A reliable and high speed computing H Aliee, HR Zarandi 2011 Proceedings-Annual Reliability and Maintainability Symposium, 1-6, 2011	32	2011
SEU-mitigation placement and routing algorithms and their impact in SRAM-based FPGAs HR Zarandi, SG Miremadi, DK Pradhan, J Mathew 8th International Symposium on Quality Electronic Design (ISQED'07), 380-385, 2007	32	2007
Multiple upsets tolerance in SRAM memory C Argyrides, HR Zarandi, DK Pradhan 2007 IEEE International Symposium on Circuits and Systems (ISCAS), 365-368, 2007	29	2007
Designing fault-tolerant network-on-chip router architecture A Eghbal, PM Yaghini, H Pedram, HR Zarandi International Journal of Electronics 97 (10), 1181-1192, 2010	27	2010
Hystery: a hybrid scheduling and mapping approach to optimize temperature, energy consumption and lifetime reliability of heterogeneous multiprocessor systems A Abdi, HR Zarandi The Journal of Supercomputing 74, 2213-2238, 2018	26	2018
Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs G Asadi, SG Miremadi, HR Zarandi, A Ejlali 10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004 …, 2004	25	2004
Quantitative assessment of risks on construction projects using fault tree analysis with hybrid uncertainties S Shoar, F Nasirzadeh, HR Zarandi Construction Innovation 19 (1), 48-70, 2019	24	2019

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