| Asic routing architecture D How, A Srinivasan, A El Gamal US Patent 6,242,767, 2001 | 109 | 2001 |
| Thermally aware design modification R Chandra, A Srinivasan, N Gopal US Patent 7,823,102, 2010 | 81 | 2010 |
| Thermal Simulation Using Adaptive 3D and Hierarchical Grid Mechanisms R Chandra, JY Shu, A Srinivasan, P Carnevali US Patent App. 12/131,821, 2008 | 55* | 2008 |
| Method for balanced-delay clock tree insertion A Srinivasan, DL Allen US Patent 6,698,006, 2004 | 53 | 2004 |
| Method for determining load capacitance A Srinivasan US Patent 7,003,741, 2006 | 51 | 2006 |
| Function block architecture for gate array A Gamal, D How, A Srinivasan | 50* | 2003 |
| Circuit optimization for minimum path timing violations A Srinivasan US Patent 7,222,318, 2007 | 46 | 2007 |
| Function block architecture for gate array D How, A Srinivasan, A El Gamal US Patent 6,014,038, 2000 | 40* | 2000 |
| Method for optimal driver selection A Srinivasan US Patent 6,754,877, 2004 | 37 | 2004 |
| Method for determining a zero-skew buffer insertion point A Srinivasan US Patent 6,701,507, 2004 | 31 | 2004 |
| Circuit optimization for minimum path timing violations A Srinivasan US Patent 6,701,505, 2004 | 31 | 2004 |
| Practical chip-centric electro-thermal simulations R Gillon, P Joris, H Oprins, B Vandevelde, A Srinivasan, R Chandra 2008 14th International Workshop on Thermal Inveatigation of ICs and Systems …, 2008 | 30 | 2008 |
| Static random access memory cell with single logic-high voltage level bit-line and address-line drivers TP Guo, A Srinivasan US Patent 5,301,147, 1994 | 28 | 1994 |
| Junction-level thermal extraction and simulation of 3DICs S Melamed, T Thorolfsson, A Srinivasan, E Cheng, P Franzon, R Davis 2009 IEEE International Conference on 3D System Integration, 1-7, 2009 | 27 | 2009 |
| Fine grain thermal modeling and experimental validation of 3D-ICs H Oprins, A Srinivasan, M Cupak, V Cherman, C Torregiani, M Stucchi, ... Microelectronics Journal 42 (4), 572-578, 2011 | 26 | 2011 |
| A 1024 pin universal interconnect array with routing architecture R Guo, H Nguyen, A Srinivasan, H Verheyen, H Cai, S Law, A Mohsen Custom Integrated Circuits Conference, 1992., Proceedings of the IEEE 1992 …, 1992 | 26 | 1992 |
| Method and apparatus for controlling and observing data in a logic block-based ASIC D How, A Srinivasan, R Osann Jr, S Mukund US Patent 6,611,932, 2003 | 24 | 2003 |
| Method and apparatus for controlling and observing data in a logic block-based asic D How, A Srinivasan, R Osann, S Mukund US Patent 6,223,313, 2001 | 24 | 2001 |
| Method for match delay buffer insertion A Srinivasan, DL Allen US Patent 6,701,506, 2004 | 19 | 2004 |
| Transient thermal analysis R Chandra, P Carnevali, JY Shu, A Srinivasan US Patent 8,019,580, 2011 | 18 | 2011 |
Abbas El GamalElectrical Engineering, Stanford UniversityPotvrđena adresa e-pošte na ee.stanford.edu
