| Efficient polyphase decomposition of comb decimation filters in/spl Sigma//spl utri/analog-to-digital converters H Aboushady, Y Dumonteix, MM Louerat, H Mehrez IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001 | 203 | 2001 |
| FPGA architectures: An overview U Farooq, Z Marrakchi, H Mehrez, U Farooq, Z Marrakchi, H Mehrez Tree-Based Heterogeneous FPGA Architectures: Application Specific …, 2012 | 191* | 2012 |
| FPGA interconnect topologies exploration Z Marrakchi, H Mrabet, U Farooq, H Mehrez International Journal of Reconfigurable Computing 2009, 2009 | 75 | 2009 |
| Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation Z Marrakchi, H Mrabet, H Mehrez 2005 International Conference on Reconfigurable Computing and FPGAs …, 2005 | 34 | 2005 |
| Exploration of heterogeneous FPGA architectures U Farooq, H Parvez, H Mehrez, Z Marrakchi International Journal of Reconfigurable Computing 2011, 1-18, 2011 | 30 | 2011 |
| Application-specific mesh-based heterogeneous FPGA architectures H Parvez, H Mehrez Springer Science & Business Media, 2010 | 29 | 2010 |
| Efficient tree topology for FPGA interconnect network M Zied, M Hayder, A Emna, M Habib Proceedings of the 18th ACM Great Lakes symposium on VLSI, 321-326, 2008 | 25 | 2008 |
| Architecture and design methodology of the RBF-DDA neural network M Aberbour, H Mehrez 1998 IEEE International Symposium on Circuits and Systems (ISCAS) 3, 199-202, 1998 | 25 | 1998 |
| Three-dimensional integration: A more than Moore technology V Pangracious, Z Marrakchi, H Mehrez, V Pangracious, Z Marrakchi, ... Three-dimensional design methodologies for tree-based FPGA architecture, 13-41, 2015 | 24 | 2015 |
| A family of redundant multipliers dedicated to fast computation for signal processing Y Dumonteix, H Mehrez 2000 IEEE International Symposium on Circuits and Systems (ISCAS) 5, 325-328, 2000 | 24 | 2000 |
| Mesh of tree: unifying mesh and MFPGA for better device performances Z Marrakchi, H Mrabet, C Masson, H Mehrez First International Symposium on Networks-on-Chip (NOCS'07), 243-252, 2007 | 21 | 2007 |
| Low Power Comb Decimation Filter Using Polyphase Decomposition for Mono-Bit Σ∆ Analog-to-Digital Converters Y Dumonteix, H Aboushady, H Mehrez, MM Louerat International Conference on Signal Processing Applications & Technology, ICSPAT, 2000 | 21 | 2000 |
| Three-Dimensional Design Methodologies for Tree-based FPGA Architecture V Pangracious, Z Marrakchi, H Mehrez Springer International Publishing, 2015 | 18 | 2015 |
| FPGA architectures: an overview, in tree-based heterogeneous FPGA architectures U Farooq, Z Marrakchi, H Mehrez, U Farooq, Z Marrakchi, H Mehrez Springer, 2012 | 18 | 2012 |
| ASIF: Application specific inflexible FPGA H Parvez, H Mehrez, H Parvez, H Mehrez Application-Specific Mesh-based Heterogeneous FPGA Architectures, 77-101, 2011 | 18 | 2011 |
| Stratus: A procedural circuit description language based upon Python S Belloeil, D Dupuis, C Masson, JP Chaput, H Mehrez 2007 Internatonal Conference on Microelectronics, 261-264, 2007 | 17 | 2007 |
| AES-GCM and AEGIS: efficient and high speed hardware implementations KM Abdellatif, R Chotin-Avot, H Mehrez Journal of Signal Processing Systems 88, 1-12, 2017 | 16 | 2017 |
| Application-specific fpga using heterogeneous logic blocks H Parvez, Z Marrakchi, A Kilic, H Mehrez ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (3), 1-14, 2011 | 16 | 2011 |
| Programmable gate array, switch box and logic unit for such an array Z Marrakchi, H Mrabet, H Mehrez US Patent 7,795,911, 2010 | 16 | 2010 |
| Performance analysis and optimization of high density tree-based 3d multilevel FPGA V Pangracious, Z Marrakchi, E Amouri, H Mehrez Reconfigurable Computing: Architectures, Tools and Applications: 9th …, 2013 | 15 | 2013 |
