| Improving the resolution of multiple defect diagnosis by removing and selecting tests N Wang, I Pomeranz, B Benware, ME Amyeen, S Venkataraman 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2018 | 18 | 2018 |
| Deepgate: Learning neural representations of logic gates M Li, S Khan, Z Shi, N Wang, H Yu, Q Xu Proceedings of the 59th ACM/IEEE Design Automation Conference, 667-672, 2022 | 15 | 2022 |
| Deeptpi: Test point insertion with deep reinforcement learning Z Shi, M Li, S Khan, L Wang, N Wang, Y Huang, Q Xu 2022 IEEE International Test Conference (ITC), 194-203, 2022 | 8 | 2022 |
| Resynthesis for avoiding undetectable faults based on design-for-manufacturability guidelines N Wang, I Pomeranz, SM Reddy, A Sinha, S Venkataraman 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 8 | 2019 |
| Accelerate sat-based atpg via preprocessing and new conflict management heuristics J Huang, HL Zhen, N Wang, M Yuan, H Mao, Y Huang, J Tao 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 365-370, 2022 | 6 | 2022 |
| On reliability of android wearable health devices N Wang, EB Yi, S Bagchi arXiv preprint arXiv:1706.09247, 2017 | 5 | 2017 |
| Tea: A test generation algorithm for designs with timing exceptions N Wang, C Wang, KH Tsai, WT Cheng, X Lin, M Kassab, I Pomeranz 2019 IEEE 28th Asian Test Symposium (ATS), 19-195, 2019 | 4 | 2019 |
| Neural fault analysis for sat-based atpg J Huang, HL Zhen, N Wang, H Mao, M Yuan, Y Huang 2022 IEEE International Test Conference (ITC), 36-45, 2022 | 3 | 2022 |
| Representation learning of logic circuits M Li, S Khan, Z Shi, N Wang, Y Huang, Q Xu 2022 59th ACM/IEEE Design Automation Conference (DAC), to appear, 2022 | 3 | 2022 |
| Layout resynthesis by applying design-for-manufacturability guidelines to avoid low-coverage areas of a cell-based design N Wang, I Pomeranz, SM Reddy, A Sinha, S Venkataraman ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (4 …, 2019 | 2 | 2019 |
| Functional broadside test generation using a commercial ATPG tool N Wang, B Yao, X Lin, I Pomeranz 2017 IEEE computer society annual symposium on VLSI (ISVLSI), 308-313, 2017 | 2 | 2017 |
| Compression-Aware ATPG X Wang, Z Wang, N Wang, W Zhang, Y Huang 2022 IEEE International Test Conference (ITC), 108-117, 2022 | 1 | 2022 |
| Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus H Zhen, M Chen, M Yuan, N Wang, W Luo, Y Huang US Patent App. 18/397,481, 2024 | | 2024 |
| GPU-Based Concurrent Static Learning H Liang, X Lin, L Lai, N Wang, Y Huang, F Yang, Y Yang 2023 IEEE International Test Conference (ITC), 159-165, 2023 | | 2023 |
| Improving Efficiency of Cell-Aware Fault Modeling By Utilizing Defect-Free Analog Simulation C Chen, W Zhang, N Wang, Y Huang 2023 International Symposium of Electronics Design Automation (ISEDA), 323-327, 2023 | | 2023 |
| Conflict-driven Structural Learning Towards Higher Coverage Rate in ATPG HL Zhen, N Wang, J Huang, X Huang, M Yuan, Y Huang arXiv preprint arXiv:2303.02290, 2023 | | 2023 |
| Deterministic test pattern generation for designs with timing exceptions WT Cheng, KH Tsai, N Wang, C Wang, X Lin, MA Kassab, I Pomeranz US Patent 10,977,400, 2021 | | 2021 |
| Test Generation and Resynthesis Procedures for Test and Diagnosis Quality N Wang Purdue University, 2019 | | 2019 |
