Encrypt flip-flop: A novel logic encryption technique for sequential circuits R Karmakar, S Chatopadhyay, R Kapur arXiv preprint arXiv:1801.04961, 2018 | 93 | 2018 |
A scan obfuscation guided design-for-security approach for sequential circuits R Karmakar, S Chattopadhyay, R Kapur IEEE Transactions on Circuits and Systems II: Express Briefs 67 (3), 546-550, 2019 | 41 | 2019 |
A new logic encryption strategy ensuring key interdependency R Karmakar, N Prasad, S Chattopadhyay, R Kapur, I Sengupta 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | 38 | 2017 |
Efficient key-gate placement and dynamic scan obfuscation towards robust logic encryption R Karmakar, H Kumar, S Chattopadhyay IEEE Transactions on Emerging Topics in Computing 9 (4), 2109-2124, 2019 | 28 | 2019 |
A cellular automata guided finite-state-machine watermarking strategy for IP protection of sequential circuits R Karmakar, SS Jana, S Chattopadhyay IEEE Transactions on Emerging Topics in Computing 10 (2), 806-823, 2020 | 21 | 2020 |
On finding suitable key-gate locations in logic encryption R Karmakar, H Kumar, S Chattopadhyay 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 20 | 2018 |
Runtime mitigation of illegal packet request attacks in networks-on-chip N Prasad, R Karmakar, S Chattopadhyay, I Chakrabarti 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 20 | 2017 |
Optimization of the IEEE 1687 access network for hybrid access schedules SS Nuthakki, R Karmakar, S Chattopadhyay, K Chakrabarty 2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016 | 16 | 2016 |
Enhancing security of logic encryption using embedded key generation unit R Karmakar, S Chattopadhyay, R Kapur 2017 International Test Conference in Asia (ITC-Asia), 131-136, 2017 | 14 | 2017 |
Theoretical computation of transmission coefficient of double quantum well triple barrier structure in presence of electric field S Mukherjee, R Karmakar, A Deyasi International Journal of Soft Computing and Engineering 1, 41-44, 2011 | 13 | 2011 |
Hardware IP protection using logic encryption and watermarking R Karmakar, S Chattopadhyay 2020 IEEE International Test Conference (ITC), 1-10, 2020 | 12 | 2020 |
Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling R Karmakar, S Chattopadhyay Integration 50, 61-73, 2015 | 12 | 2015 |
Thermal-aware test data compression using dictionary based coding R Karmakar, S Chattopadhyay 2015 28th International Conference on VLSI Design, 53-58, 2015 | 11 | 2015 |
A particle swarm optimization guided approximate key search attack on logic locking in the absence of scan access R Karmakar, S Chattopadhyay 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 448-453, 2020 | 10 | 2020 |
A cellular automata guided obfuscation strategy for finite-state-machine synthesis R Karmakar, SS Jana, S Chattopadhyay Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 9 | 2019 |
Calculating transmission coefficient of double quantum well triple barrier structure having parabolic geometry using propagation matrix method R Karmakar, A Biswas, S Mukherjee, A Deyasi IJEAT 1, 37-41, 2011 | 9 | 2011 |
On securing scan obfuscation strategies against ScanSAT attack R Karmakar, S Chattopadhyay 2020 21st International Symposium on Quality Electronic Design (ISQED), 213-218, 2020 | 8 | 2020 |
Testing of 3d-stacked ics with hard-and soft-dies-a particle swarm optimization based approach R Karmakar, A Agarwal, S Chattopadhyay 2015 IEEE 33rd VLSI Test Symposium (VTS), 1-6, 2015 | 7 | 2015 |
Improving security of logic encryption in presence of design-for-testability infrastructure R Karmakar, S Chattopadhyay, M Chakraborty 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 5 | 2019 |
Thermal-Safe Schedule Generation For System-on-Chip Testing R Karmakar, S Chattopadhyay VLSI Design (VLSID), 2016 29th International Conference on, 2016 | 5 | 2016 |