| BYOC: a" bring your own core" framework for heterogeneous-ISA research J Balkind, K Lim, M Schaffner, F Gao, G Chirkov, A Li, A Lavrov, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 60 | 2020 |
| PRGA: An Open-Source FPGA Research and Prototyping Framework A Li, D Wentzlaff The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays …, 2021 | 29 | 2021 |
| OpenPiton at 5: A Nexus for open and agile hardware design J Balkind, TJ Chang, PJ Jackson, G Tziantzioulis, A Li, F Gao, A Lavrov, ... IEEE Micro 40 (4), 22-31, 2020 | 19 | 2020 |
| Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes D Zhang, S Li, A Li, Y Liu, XS Hu, H Yang 2014 IEEE 32nd International Conference on Computer Design (ICCD), 348-354, 2014 | 18 | 2014 |
| PRGA: An open-source framework for building and using custom FPGAs A Li, D Wentzlaff The First Workshop on Open-Source Design Automation; Florence, Italy, 1-6, 2019 | 12 | 2019 |
| DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including … F Gao, TJ Chang, A Li, M Orenes-Vera, D Giri, PJ Jackson, A Ning, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 11 | 2023 |
| Duet: Creating Harmony between Processors and Embedded FPGAs A Li, A Ning, D Wentzlaff 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 6 | 2023 |
| Cycle-free FPGA routing graphs A Li, D Wentzlaff Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020 | 6 | 2020 |
| Automated Design of FPGAs Facilitated by Cycle-Free Routing A Li, TJ Chang, D Wentzlaff 2020 30th International Conference on Field-Programmable Logic and …, 2020 | 5 | 2020 |
| Nonvolatile memory allocation and hierarchy optimization for high-level synthesis S Li, A Li, Y Liu, Y Xie, H Yang The 20th Asia and South Pacific Design Automation Conference, 166-171, 2015 | 5 | 2015 |
| CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA TJ Chang, A Li, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 4 | 2023 |
| Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations S Li, A Li, Y Zhe, Y Liu, P Li, G Sun, Y Wang, H Yang, Y Xie 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 4 | 2015 |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 2 | 2023 |
| Redwood: Flexible and Portable Heterogeneous Tree Traversal Workloads Y Xu, A Li, T Sorensen 2023 IEEE International Symposium on Performance Analysis of Systems and …, 2023 | 1 | 2023 |
| OpenPiton: An Emerging Standard for Open-Source EDA Tool Development J Balkind, A Lavrov, M McKeown, Y Fu, T Nguyen, M Shahrad, A Li, K Lim, ... | | |
| Evaluating Shared Memory Heterogeneous Systems Using Traverse-compute Workloads Y Xu, A Li, T Sorensen | | |
