Prati
Seth H Pugsley
Seth H Pugsley
Research Scientist, Intel Labs
Potvrđena adresa e-pošte na cs.utah.edu
Naslov
Citirano
Citirano
Godina
NDC: Analyzing the impact of 3D-stacked memory+ logic devices on MapReduce workloads
SH Pugsley, J Jestes, H Zhang, R Balasubramonian, V Srinivasan, ...
2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014
3012014
Usimm: the utah simulated memory module
N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ...
University of Utah, Tech. Rep, 1-24, 2012
1842012
Efficiently prefetching complex address patterns
M Shevgoor, S Koladiya, R Balasubramonian, C Wilkerson, SH Pugsley, ...
Proceedings of the 48th International Symposium on Microarchitecture, 141-152, 2015
1532015
Path confidence based lookahead prefetching
J Kim, SH Pugsley, PV Gratz, ALN Reddy, C Wilkerson, Z Chishti
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
1232016
Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers
SH Pugsley, Z Chishti, C Wilkerson, P Chuang, RL Scott, A Jaleel, SL Lu, ...
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
1172014
SWEL: Hardware cache coherence protocols to map shared data onto shared caches
SH Pugsley, JB Spjut, DW Nellans, R Balasubramonian
Proceedings of the 19th international conference on Parallel architectures …, 2010
842010
Comparing implementations of near-data computing with in-memory mapreduce workloads
SH Pugsley, J Jestes, R Balasubramonian, V Srinivasan, ...
IEEE Micro 34 (4), 44-52, 2014
802014
Perceptron-based prefetch filtering
E Bhatia, G Chacon, S Pugsley, E Teran, PV Gratz, DA Jiménez
Proceedings of the 46th International Symposium on Computer Architecture, 1-13, 2019
632019
Scalable and reliable communication for hardware transactional memory
SH Pugsley, M Awasthi, N Madan, N Muralimanohar, R Balasubramonian
Proceedings of the 17th international conference on Parallel architectures …, 2008
552008
Kill the program counter: Reconstructing program behavior in the processor cache hierarchy
J Kim, E Teran, PV Gratz, DA Jiménez, SH Pugsley, C Wilkerson
ACM SIGPLAN Notices 52 (4), 737-749, 2017
492017
Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller
A Gundu, G Sreekumar, A Shafiee, S Pugsley, H Jain, ...
Proceedings of the Third Workshop on Hardware and Architectural Support for …, 2014
222014
Usimm: the utah simulated memory module a simulation infrastructure for the jwac memory scheduling championship
N Chatterjee, R Balasubramonian, M Shevgoor, SH Pugsley, AN Udipi, ...
Utah and Intel Corp, 2012
222012
Fixed-function hardware sorting accelerators for near data mapreduce execution
SH Pugsley, A Deb, R Balasubramonian, F Li
2015 33rd IEEE International Conference on Computer Design (ICCD), 439-442, 2015
192015
Spiking neural network accelerator using external memory
B Akin, S Pugsley
US Patent App. 15/853,282, 2019
162019
Instruction and logic for run-time evaluation of multiple prefetchers
ZA Chishti, CB Wilkerson, S Pugsley, PF Chuang, RL Scott, A Jaleel, ...
US Patent 9,378,021, 2016
142016
Perceptron-based prefetch filtering. In 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA)
E Bhatia, G Chacon, S Pugsley, E Teran, PV Gratz, DA Jiménez
IEEE, 1ś13, 2019
122019
Optimizing a multi-core processor for message-passing workloads
N Chatterjee, SH Pugsley, J Spjut, R Balasubramonian
Proceedings of the Workshop on Unique Chips and Systems (UCAS-5), 2009
112009
Method and system for coordinating baseline and secondary prefetchers
SH Pugsley, M Shevgoor, CB Wilkerson
US Patent 10,678,692, 2020
82020
Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register
G Venkatesh, CB Wilkerson, SH Pugsley, DT Marr
US Patent 10,452,551, 2019
72019
Method and apparatus for pre-fetching data in a system having a multi-level system memory
Z Wang, CB Wilkerson, ZA Chishti, SH Pugsley, AR Alameldeen, SLL Lu
US Patent 10,108,549, 2018
62018
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