| FIR filter realization via deferred end-around carry modular addition A Belghadr, G Jaberipur IEEE Transactions on Circuits and Systems I: Regular Papers 65 (9), 2878-2888, 2018 | 18 | 2018 |
| Fast division in the residue number system {2n+ 1, 2n, 2n-1} based on shortcut mixed radix conversion Z Torabi, G Jaberipur, A Belghadr Computers & Electrical Engineering 83, 106571, 2020 | 11 | 2020 |
| Impact of diminished-1 encoding on residue number systems arithmetic units and converters G Jaberipur, A Belghadr, S Nejati Computers & Electrical Engineering 75, 61-76, 2019 | 9 | 2019 |
| Three-dimensional physical design flow for monolithic 3D-FPGAs to improve timing closure and chip area A Belghadr, A Jahanian Journal of Circuits, Systems and Computers 26 (10), 1750154, 2017 | 4 | 2017 |
| (5+ 2⌈ log n⌉) ΔG diminished-1 modulo-(2n+ 1) unified adder/subtractor with full zero handling G Jaberipur, A Belghadr Computers & Electrical Engineering 61, 95-103, 2017 | 4 | 2017 |
| Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs A Belghadr, A Jahanian Integration 47 (1), 96-104, 2014 | 3 | 2014 |
| Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set A Belghadr, G Jaberipur Signal, Image and Video Processing 16 (6), 1443-1454, 2022 | 2 | 2022 |
| An RNS Comparator via Dynamic Range Partitioning: The Case of {2n-1, 2n, 2 n+ 1-1} Z Torabi, A Belghadr THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING 16 (2), 38-43, 2019 | 2 | 2019 |
| Fast and Power Efficient Signed/Unsigned RNS Comparator & Sign Detector Z Torabi, A Belghadr Journal of Electrical and Computer Engineering Innovations (JECEI) 11 (1), 41-50, 2023 | | 2023 |
| Low-Power CMOS/Nanomaterial Three-Dimensional Field Programmable Gate Array Architecture H Sharifi, F Sharifi, A Belghadr Quantum Matter 5 (4), 612-615, 2016 | | 2016 |
Ghassem JaberipurProfessor for the Brain Pool Program in Chosun University, Gwangju, South Korea, SBU retiredVerified email at sbu.ac.ir
