Magnus Själander
Magnus Själander
Associate Professor, Norwegian University of Science (NTNU) and Visiting Senior Lecturer at Uppsala
Verified email at - Homepage
Cited by
Cited by
EPIC: An energy-efficient, high-performance GPGPU computing research infrastructure
M Själander, M Jahre, G Tufte, N Reissmann
arXiv preprint arXiv:1912.05848, 2019
Bismo: A scalable bit-serial matrix multiplication overlay for reconfigurable computing
Y Umuroglu, L Rasnayake, M Själander
2018 28th International Conference on Field Programmable Logic and …, 2018
A high-speed, energy-efficient two-cycle multiply-accumulate (MAC) architecture and its application to a double-throughput MAC unit
TT Hoang, M Sjalander, P Larsson-Edefors
Circuits and Systems I: Regular Papers, IEEE Transactions on 57 (12), 3073-3081, 2010
Efficient invisible speculative execution through selective delay and value prediction
C Sakalis, S Kaxiras, A Ros, A Jimborean, M Själander
2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture …, 2019
FlexCore: Utilizing exposed datapath control for efficient computing
M Thuresson, M Själander, M Björk, L Svensson, P Larsson-Edefors, ...
Journal of Signal Processing Systems 57 (1), 5-19, 2009
Multiplication acceleration through twin precision
M Sjalander, P Larsson-Edefors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (9 …, 2009
A look-ahead task management unit for embedded multi-core architectures
M Själander, A Terechko, M Duranton
Digital System Design Architectures, Methods and Tools, 2008. DSD'08. 11th …, 2008
High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree
M Sjalander, P Larsson-Edefors
2008 15th IEEE International Conference on Electronics, Circuits and Systems …, 2008
Multiplier reduction tree with logarithmic logic depth and regular connectivity
H Eriksson, P Larsson-Edefors, M Sheeran, M Sjalander, D Johansson, ...
2006 IEEE International Symposium on Circuits and Systems, 4 pp.-8, 2006
The Case for HPM-Based Baugh-Wooley Multipliers
M Själander, P Larson-Edefors
Chalmers University of Technology, Sweden, 2008
Power-efficient computer architectures: Recent advances
M Själander, M Martonosi, S Kaxiras
Synthesis Lectures on Computer Architecture 9 (3), 1-96, 2014
An LTE Uplink Receiver PHY Benchmark and Subframe-Based Power Management
M Själander, SA McKee, P Brauer, D Engdal, A Vajda
IEEE International Symposium on Performance Analysis of Systems and Software …, 2012
Next Generation Multi-Purpose Microprocessor
J Andersson, M Själander, J Gaisler
Data Systems In Aerospace (DASIA 2010), 2010
A low-leakage twin-precision multiplier using reconfigurable power gating
M Sjalander, M Drazdziulis, P Larsson-Edefors, H Eriksson
2005 IEEE International Symposium on Circuits and Systems (ISCAS), 1654-1657, 2005
An efficient twin-precision multiplier
M Sjalander, H Eriksson, P Larsson-Edefors
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
Twig: Multi-agent task management for colocated latency-critical cloud services
R Nishtala, V Petrucci, P Carpenter, M Sjalander
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
Clairvoyance: Look-ahead compile-time scheduling
KA Tran, TE Carlson, K Koukos, M Själander, V Spiliopoulos, S Kaxiras, ...
2017 IEEE/ACM International Symposium on Code Generation and Optimization …, 2017
Designing a practical data filter cache to improve both energy efficiency and performance
A Bardizbanyan, M Själander, D Whalley, P Larsson-Edefors
ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-25, 2013
Speculative tag access for reduced energy dissipation in set-associative L1 data caches
A Bardizbanyan, M Själander, D Whalley, P Larsson-Edefors
Computer Design (ICCD), 2013 IEEE 31st International Conference on, 302-308, 2013
Early results from ERA—Embedded Reconfigurable Architectures
S Wong, A Brandon, F Anjam, R Seedorf, R Giorgi, Z Yu, N Puzovic, ...
Industrial Informatics (INDIN), 2011 9th IEEE International Conference on …, 2011
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