Aritra Hazra

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	Sve	Od 2019.
Citati	371	259
H-indeks	10	9
i10-indeks	12	7

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Pallab DasguptaIndian Institute of Technology KharagpurPotvrđena adresa e-pošte na cse.iitkgp.ac.in
Debdeep MukhopadhyayProfessor, Dept of Computer Science and Engineering, IIT Kharagpur, IndiaPotvrđena adresa e-pošte na cse.iitkgp.ac.in
Durba ChatterjeePostdoctoral Researcher, Radboud UniversityPotvrđena adresa e-pošte na ru.nl
Chester RebeiroIndian Institute of Technology MadrasPotvrđena adresa e-pošte na cs.columbia.edu
Swarup BhuniaUniversity of FloridaPotvrđena adresa e-pošte na ece.ufl.edu
Sayandeep SanyalStaff R&D Engineer, SynopsysPotvrđena adresa e-pošte na ieee.org
soumyajit deyAssistant Professor, Computer Science, IIT KharagpurPotvrđena adresa e-pošte na cse.iitkgp.ernet.in
Sudipa MandalPh.D student of Computer Science and Engineering Department, IIT KharagpurPotvrđena adresa e-pošte na cse.iitkgp.ernet.in
Keerthi KPhD Research Scholar, IIT MadrasPotvrđena adresa e-pošte na smail.iitm.ac.in
Ansuman BanerjeeProfessor, Indian Statistical InstitutePotvrđena adresa e-pošte na isical.ac.in
Urbi ChatterjeeAssistant Professor, CSE, IIT Kanpur and Alumni, SEAL, IIT KharagpurPotvrđena adresa e-pošte na cse.iitk.ac.in
Punit KhannaIndian Institute of Technology MadrasPotvrđena adresa e-pošte na cse.iitm.ac.in
Boyapally HarishmaPhD StudentPotvrđena adresa e-pošte na iitkgp.ac.in
Sikhar PatranabisIBM Research IndiaPotvrđena adresa e-pošte na ibm.com
Antonio Anastasio Bruto da CostaPrincipal Engineer, WMG, University of WarwickPotvrđena adresa e-pošte na warwick.ac.uk
Sahil GoyalComputer Science and Engineering, University of California San DiegoPotvrđena adresa e-pošte na cs.ucsd.edu
Saurav Kumar GhoshIntel CorporationPotvrđena adresa e-pošte na intel.com
Satya Gautam VadlamudiElystar Investment ManagementPotvrđena adresa e-pošte na elystarinvest.com
Milind SrivastavaCarnegie Mellon UniversityPotvrđena adresa e-pošte na andrew.cmu.edu
Patanjali SLPSKUniversity of FloridaPotvrđena adresa e-pošte na ufl.edu

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Aritra Hazra

Department of Computer Science and Engineering, IIT Kharagpur

Potvrđena adresa e-pošte na cse.iitkgp.ac.in - Početna stranica

Formal Methods Design Verification CAD for Security Artificial Intelligence Machine Learning


Naslov Poredaj po navodima Poredaj po godini Poredaj po naslovu	Citirano Citirano	Godina
XFC: A framework for exploitable fault characterization in block ciphers P Khanna, C Rebeiro, A Hazra Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017	50	2017
SAFARI: Automatic synthesis of fault-attack resistant block cipher implementations I Roy, C Rebeiro, A Hazra, S Bhunia IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019	27	2019
Formal verification of architectural power intent A Hazra, S Goyal, P Dasgupta, A Pal IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (1), 78-91, 2012	27	2012
Formal verification for security in IoT devices K Keerthi, I Roy, A Hazra, C Rebeiro Security and fault tolerance in internet of things, 179-200, 2019	23	2019
PUF-G: A CAD framework for automated assessment of provable learnability from formal PUF representations D Chatterjee, D Mukhopadhyay, A Hazra Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020	22	2020
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent A Hazra, S Mitra, P Dasgupta, A Pal, D Bagchi, K Guha Proceedings of the 47th Design Automation Conference, 773-776, 2010	22	2010
Interpose PUF can be PAC learned D Chatterjee, D Mukhopadhyay, A Hazra Cryptology ePrint Archive, 2020	17	2020
SOLOMON: An automated framework for detecting fault attack vulnerabilities in hardware M Srivastava, P Slpsk, I Roy, C Rebeiro, A Hazra, S Bhunia 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 310-313, 2020	15	2020
POWER-TRUCTOR: An integrated tool flow for formal verification and coverage of architectural power intent A Hazra, R Mukherjee, P Dasgupta, A Pal, KM Harer, A Banerjee, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013	14	2013
Physically related functions: Exploiting related inputs of PUFs for authenticated-key exchange D Chatterjee, H Boyapally, S Patranabis, U Chatterjee, A Hazra, ... IEEE Transactions on Information Forensics and Security 17, 3847-3862, 2022	12	2022
Formal verification of power management logic with mixed-signal domains S Mandal, AB Da Costa, A Hazra, P Dasgupta, B Naware, RM Chunduri, ... 2017 30th International Conference on VLSI Design and 2017 16th …, 2017	10	2017
Cohesive coverage management for simulation and formal property verification A Hazra, A Banerjee, S Mitra, P Dasgupta, PP Chakrabarti, CR Mohan 2008 IEEE Computer Society Annual Symposium on VLSI, 251-256, 2008	10	2008
SACReD: An attack framework on SAC resistant delay-PUFs leveraging bias and reliability factors D Chatterjee, U Chatterjee, D Mukhopadhyay, A Hazra 2021 58th ACM/IEEE Design Automation Conference (DAC), 85-90, 2021	9	2021
FEDS: Comprehensive fault attack exploitability detection for software implementations of block ciphers K Keerthi, I Roy, C Rebeiro, A Hazra, S Bhunia IACR Transactions on Cryptographic Hardware and Embedded Systems, 272-299, 2020	9	2020
Formal methods for early analysis of functional reliability in component-based embedded applications A Hazra, P Ghosh, SG Vadlamudi, PP Chakrabarti, P Dasgupta IEEE Embedded systems letters 5 (1), 8-11, 2013	9	2013
Synthesis of sampling modes for adaptive control R Raha, A Hazra, A Mondal, S Dey, PP Chakrabarti, P Dasgupta 2014 IEEE International Conference on Control System, Computing and …, 2014	8	2014
Formal assessment of reliability specifications in embedded cyber-physical systems A Hazra, P Dasgupta, PP Chakrabarti Journal of Applied Logic 18, 71-104, 2016	7	2016
Reliability guarantees in automata-based scheduling for embedded control software A Hazra, P Dasgupta IEEE Embedded Systems Letters 5 (2), 17-20, 2013	7	2013
Covert: A coverage reporting tool for analog mixed-signal designs S Sanyal, A Hazra, P Dasgupta, S Morrison, S Surendran, ... 2020 33rd International Conference on VLSI Design and 2020 19th …, 2020	6	2020
Formal methods for coverage analysis of architectural power states in power-managed designs A Hazra, P Dasgupta, A Banerjee, K Harer 17th Asia and South Pacific Design Automation Conference, 585-590, 2012	6	2012

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