| Evaluating the security of logic encryption algorithms P Subramanyan, S Ray, S Malik Hardware Oriented Security and Trust (HOST), 2015 IEEE International …, 2015 | 745 | 2015 |
| Malware detection using machine learning based analysis of virtual memory access patterns Z Xu, S Ray, P Subramanyan, S Malik 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 169-174, 2017 | 126 | 2017 |
| Mapping into LUT structures S Ray, A Mishchenko, N Een, R Brayton, S Jang, C Chen Proceedings of the Conference on Design, Automation and Test in Europe, 1579 …, 2012 | 50 | 2012 |
| Template-based synthesis of instruction-level abstractions for SoC verification P Subramanyan, Y Vizel, S Ray, S Malik Proceedings of the 15th Conference on Formal Methods in Computer-Aided …, 2015 | 39 | 2015 |
| ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. AV Karthik, S Ray, P Nuzzo, A Mishchenko, RK Brayton, J Roychowdhury ASP-DAC, 250-255, 2014 | 35 | 2014 |
| Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware BY Huang, S Ray, A Gupta, JM Fung, S Malik Proceedings of the 55th Annual Design Automation Conference, 91, 2018 | 33 | 2018 |
| Scalable progress verification in credit-based flow-control systems S Ray, RK Brayton 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 905-910, 2012 | 22 | 2012 |
| An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors MR Fadiheh, A Wezel, J Mueller, J Bormann, S Ray, JM Fung, S Mitra, ... arXiv preprint arXiv:2108.01979, 2021 | 17 | 2021 |
| Formal verification of security critical hardware-firmware interactions in commercial SoCs S Ray, N Ghosh, RJ Masti, A Kanuparthi, JM Fung 2019 56th ACM/IEEE Design Automation Conference (DAC), 1-4, 2019 | 14 | 2019 |
| Enhancing ABC for LTL Stabilization Verification of SystemVerilog/VHDL Models J Long, S Ray, B Sterin, A Mishchenko, R Brayton Ganesh Gopalakrishnan University of Utah USA, 38, 2011 | 12 | 2011 |
| BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies AV Karthik, S Ray, J Roychowdhury The 20th Asia and South Pacific Design Automation Conference, 366-371, 2015 | 9 | 2015 |
| Verification of authenticated firmware loaders SK Muduli, P Subramanyan, S Ray 2019 Formal Methods in Computer Aided Design (FMCAD), 110-119, 2019 | 7 | 2019 |
| A dynamic assertion-based verification platform for validation of UML designs A Banerjee, S Ray, P Dasgupta, PP Chakrabarti, S Ramesh, P Vignesh, ... ACM SIGSOFT Software Engineering Notes 37 (1), 1-14, 2012 | 7 | 2012 |
| A dynamic assertion-based verification platform for UML statecharts over rhapsody A Banerjee, S Ray, P Dasgupta, PP Chakrabarti, S Ramesh, P Vignesh, ... TENCON 2008-2008 IEEE Region 10 Conference, 1-6, 2008 | 6 | 2008 |
| Minimum-perturbation retiming for delay optimization S Ray, A Mishchenko, R Brayton, S Jang, T Daniel Proc. IWLS’10, 2010 | 5 | 2010 |
| Incremental sequential equivalence checking and subgraph isomorphism S Ray, A Mishchenko, R Brayton | 4 | 2009 |
| Well-foundedness in Credit-Based Flow-Control Systems S Ray, RK Brayton International Workshop on Logic Synthesis, 1-8, 2012 | 3 | 2012 |
| A Dynamic Assertion-Based Verification Platform for Validation of UML Designs A Banerjee, S Ray, P Dasgupta, PP Chakrabarti, S Ramesh, ... International Symposium on Automated Technology for Verification and …, 2008 | 2 | 2008 |
| A new pseudo-boolean satisfiability based approach to power mode schedulability analysis S Ray, P Dasgupta, PP Chakrabarti 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 2 | 2007 |
| Ranking structure in communication fabrics S Ray, RK Brayton Formal Methods and Models for Codesign (MEMOCODE), 2013 Eleventh IEEE/ACM …, 2013 | 1 | 2013 |
Sharad MalikProfessor of Electrical and Computer Engineering, Princeton UniversityPotvrđena adresa e-pošte na princeton.edu
