| Constructing online testable circuits using reversible logic SN Mahammad, K Veezhinathan IEEE transactions on instrumentation and measurement 59 (1), 101-109, 2009 | 196 | 2009 |
| Efficient building blocks for reversible sequential circuit design SKS Hari, S Shroff, SN Mahammad, V Kamakoti 2006 49th IEEE International Midwest Symposium on Circuits and Systems 1 …, 2006 | 105 | 2006 |
| LFSR based stream ciphers are vulnerable to power attacks S Burman, D Mukhopadhyay, K Veezhinathan Progress in Cryptology–INDOCRYPT 2007: 8th International Conference on …, 2007 | 63 | 2007 |
| A bus encoding technique for power and cross-talk minimization P Subrahmanya, R Manimegalai, V Kamakoti, M Mutyam 17th International Conference on VLSI Design. Proceedings., 443-448, 2004 | 60 | 2004 |
| Shakti-T: A RISC-V processor with light weight security extensions A Menon, S Murugan, C Rebeiro, N Gala, K Veezhinathan Proceedings of the Hardware and Architectural Support for Security and …, 2017 | 56 | 2017 |
| SHAKTI processors: An open-source hardware initiative N Gala, A Menon, R Bodduna, GS Madhusudan, V Kamakoti 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 50 | 2016 |
| Glitch-aware pattern generation and optimization framework for power-safe scan test VR Devanathan, CP Ravikumar, V Kamakoti 25th IEEE VLSI Test Symposium (VTS'07), 167-172, 2007 | 50 | 2007 |
| Dynamic coding technique for low-power data bus M Madhu, VS Murty, V Kamakoti IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 252-253, 2003 | 47 | 2003 |
| SHAKTI-F: A fault tolerant microprocessor architecture S Gupta, N Gala, GS Madhusudan, V Kamakoti 2015 IEEE 24th Asian Test Symposium (ATS), 163-168, 2015 | 44 | 2015 |
| System-on-programmable-chip implementation for on-line face recognition AP Kumar, V Kamakoti, S Das Pattern Recognition Letters 28 (3), 342-349, 2007 | 40 | 2007 |
| Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER R Bodduna, V Ganesan, P Slpsk, K Veezhinathan, C Rebeiro IEEE Computer Architecture Letters 19 (1), 9-12, 2020 | 38 | 2020 |
| Ultra folded high-speed architectures for Reed Solomon decoders K Seth, KN Viswajith, S Srinivasan, V Kamakoti 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 36 | 2006 |
| Karna: A gate-sizing based security aware EDA flow for improved power side-channel attack protection P Slpsk, PK Vairam, C Rebeiro, V Kamakoti 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 34 | 2019 |
| The Implications of Shared Data Synchronization Techniques on {Multi-Core} Energy {Efficiency} A Gautham, K Korgaonkar, P Slpsk, S Balachandran, K Veezhinathan 2012 Workshop on Power-Aware Computing and Systems (HotPower 12), 2012 | 34 | 2012 |
| On power-profiling and pattern generation for power-safe scan tests VR Devanathan, CP Ravikumar, V Kamakoti 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 34 | 2007 |
| Face recognition using weighted modular principle component analysis AP Kumar, S Das, V Kamakoti Neural Information Processing: 11th International Conference, ICONIP 2004 …, 2004 | 33 | 2004 |
| A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test VR Devanathan, CP Ravikumar, V Kamakoti 2007 IEEE International Test Conference, 1-10, 2007 | 32 | 2007 |
| Power virus generation using behavioral models of circuits K Najeeb, V Vardhan, R Konda, S Kumar, S Hari, V Kamakoti, VM Vedula 25th IEEE VLSI Test Symposium (VTS'07), 35-42, 2007 | 31 | 2007 |
| PMScan: A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test VR Devanathan, CP Ravikumar, R Mehrotra, V Kamakoti 2007 IEEE International Test Conference, 1-9, 2007 | 30 | 2007 |
| Detecting SEU-caused routing errors in SRAM-based FPGAs ESS Reddy, V Chandrasekhar, M Sashikánth, V Kamakoti, ... 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 30 | 2005 |
