| Security evaluation of WDDL and SecLib countermeasures against power attacks S Guilley, L Sauvage, P Hoogvorst, R Pacalet, GM Bertoni, S Chaudhuri IEEE Transactions on Computers 57 (11), 1482-1497, 2008 | 70 | 2008 |
| Cross-point architecture for spin-transfer torque magnetic random access memory W Zhao, S Chaudhuri, C Accoto, JO Klein, C Chappert, P Mazoyer IEEE Transactions on Nanotechnology 11 (5), 907-917, 2012 | 57 | 2012 |
| Shall we trust WDDL? S Guilley, S Chaudhuri, L Sauvage, T Graba, JL Danger, P Hoogvorst, ... Future of Trust in Computing: Proceedings of the First International …, 2009 | 41 | 2009 |
| Place-and-route impact on the security of DPL designs in FPGAs S Guilley, S Chaudhuri, L Sauvage, T Graba, JL Danger, P Hoogvorst, ... 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, 26-32, 2008 | 41 | 2008 |
| Efficient modeling and floorplanning of embedded-FPGA fabric S Chaudhuri, JL Danger, S Guilley 2007 International Conference on Field Programmable Logic and Applications …, 2007 | 23 | 2007 |
| High density spin-transfer torque (STT)-MRAM based on cross-point architecture W Zhao, S Chaudhuri, C Accoto, JO Klein, D Ravelosona, C Chappert, ... 2012 4th IEEE International Memory Workshop, 1-4, 2012 | 20 | 2012 |
| Physical design of FPGA interconnect to prevent information leakage S Chaudhuri, S Guilley, P Hoogvorst, JL Danger, T Beyrouthy, ... International Workshop on Applied Reconfigurable Computing, 87-98, 2008 | 20 | 2008 |
| FASE: an open run-time reconfigurable FPGA architecture for tamper-resistant and secure embedded systems S Chaudhuri, JL Danger, S Guilley, P Hoogvorst 2006 IEEE International Conference on Reconfigurable Computing and FPGA's …, 2006 | 20 | 2006 |
| An 8x8 run-time reconfigurable FPGA embedded in a SoC S Chaudhuri, S Guilley, F Flament, P Hoogvorst, JL Danger Proceedings of the 45th annual Design Automation Conference, 120-125, 2008 | 18 | 2008 |
| A novel asynchronous e-FPGA architecture for security applications T Beyrouthy, A Razafindraibe, L Fesquet, M Renaudin, S Chaudhuri, ... 2007 International Conference on Field-Programmable Technology, 369-372, 2007 | 17 | 2007 |
| A security vulnerability analysis of SoCFPGA architectures S Chaudhuri Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 16 | 2018 |
| Design of TAS-MRAM prototype for NV embedded memory applications S Chaudhuri, W Zhao, JO Klein, C Chappert, P Mazoyer 2010 IEEE International Memory Workshop, 1-4, 2010 | 13 | 2010 |
| A two-stage variation-aware placement method for FPGAs exploiting variation maps classification Z Guan, JSJ Wong, S Chaudhuri, G Constantinides, PYK Cheung 22nd International Conference on Field Programmable Logic and Applications …, 2012 | 12 | 2012 |
| Beyond bits: A quaternary FPGA architecture using multi-VT multi-Vdd FDSOI devices S Chaudhuri 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 38-43, 2018 | 9 | 2018 |
| High density asynchronous LUT based on non-volatile MRAM technology S Chaudhuri, W Zhao, JO Klein, C Chappert, P Mazoyer 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 9 | 2010 |
| A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. P Hoogvorst, S Guilley, S Chaudhuri, A Razafindraibe, T Beyrouthy, ... ReCoSoC, 15-22, 2007 | 8 | 2007 |
| Logical memory architecture, in particular for MRAM, PCRAM, or RRAM W Zhao, S Chaudhuri, C Chappert, JO Klein US Patent 9,305,607, 2016 | 7 | 2016 |
| Design of embedded mram macros for memory-in-logic applications S Chaudhuri, W Zhao, JO Klein, C Chappert, P Mazoyer Proceedings of the 20th symposium on Great lakes symposium on VLSI, 155-158, 2010 | 7 | 2010 |
| Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks S Guilley, S Chaudhuri, L Sauvage, JL Danger, T Beyrouthy, L Fesquet 2009 16th IEEE International Conference on Electronics, Circuits and Systems …, 2009 | 7 | 2009 |
| Efficient tiling patterns for reconfigurable gate arrays S Chaudhuri, S Guilley, P Hoogvorst, JL Danger Proceedings of the 2008 international workshop on System level interconnect …, 2008 | 7 | 2008 |
Sylvain GUILLEYTELECOM-ParisTechPotvrđena adresa e-pošte na secure-ic.com
