| Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover D Abedi, G Jaberipur, M Sangsefidi IEEE transactions on nanotechnology 14 (3), 497-504, 2015 | 267 | 2015 |
| Binary-coded decimal digit multipliers G Jaberipur, A Kaivani IET Computers & Digital Techniques 1 (4), 377-381, 2007 | 100 | 2007 |
| Improving the speed of parallel decimal multiplication G Jaberipur, A Kaivani IEEE Transactions on Computers 58 (11), 1539-1552, 2009 | 98 | 2009 |
| Improved CMOS (4; 2) compressor designs for parallel multipliers A Pishvaie, G Jaberipur, A Jahanian Computers & Electrical Engineering 38 (6), 1703-1716, 2012 | 60 | 2012 |
| Decimal full adders specially designed for quantum-dot cellular automata D Abedi, G Jaberipur IEEE Transactions on Circuits and Systems II: Express Briefs 65 (1), 106-110, 2017 | 55 | 2017 |
| A fully redundant decimal adder and its application in parallel decimal multipliers S Gorgin, G Jaberipur Microelectronics Journal 40 (10), 1471-1481, 2009 | 51 | 2009 |
| Unified Approach to the Design of Modulo-(2^ n+/-1) Adders Based on Signed-LSB Representation of Residues G Jaberipur, B Parhami 2009 19th IEEE Symposium on Computer Arithmetic, 57-64, 2009 | 46 | 2009 |
| Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems G Jaberipur, B Parhami, M Ghodsi IEEE Transactions on Circuits and Systems I: Regular Papers 52 (7), 1348-1357, 2005 | 46 | 2005 |
| High-performance CMOS (4: 2) compressors A Pishvaie, G Jaberipur, A Jahanian International journal of electronics 101 (11), 1511-1525, 2014 | 39 | 2014 |
| Fully redundant decimal arithmetic S Gorgin, G Jaberipur 2009 19th IEEE Symposium on Computer Arithmetic, 145-152, 2009 | 37 | 2009 |
| Redesigned CMOS (4; 2) compressor for fast binary multipliers A Pishvaie, G Jaberipur, A Jahanian Canadian Journal of Electrical and Computer Engineering 36 (3), 111-115, 2013 | 28 | 2013 |
| A New Residue Number System with 5-Moduli Set: {22q, 2q±3, 2q±1} H Ahmadifar, G Jaberipur The Computer Journal 58 (7), 1548-1565, 2015 | 27 | 2015 |
| Balanced minimal latency RNS addition for moduli set {2n−1, 2n, 2n+1} G Jaberipur, S Nejati 2011 18th International Conference on Systems, Signals and Image Processing, 1-7, 2011 | 27 | 2011 |
| Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits G Jaberipur, B Parhami IET computers & digital techniques 6 (5), 259-268, 2012 | 26 | 2012 |
| Constant-time addition with hybrid-redundant numbers: Theory and implementations G Jaberipur, B Parhami Integration 41 (1), 49-64, 2008 | 26 | 2008 |
| Low-power/cost RNS comparison via partitioning the dynamic range Z Torabi, G Jaberipur IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015 | 25 | 2015 |
| High radix signed digit number systems: representation paradigms G JABERIPOUR, M Ghodsi SCIENTIA IRANICA 10 (4), 383-391, 2003 | 23 | 2003 |
| Majority-Logic, its applications, and atomic-scale embodiments B Parhami, D Abedi, G Jaberipur Computers & Electrical Engineering 83, 106562, 2020 | 22 | 2020 |
| On building general modular adders from standard binary arithmetic components G Jaberipur, B Parhami, S Nejati 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals …, 2011 | 21 | 2011 |
| Adapting computer arithmetic structures to sustainable supercomputing in low-power, majority-logic nanotechnologies G Jaberipur, B Parhami, D Abedi IEEE Transactions on Sustainable Computing 3 (4), 262-273, 2018 | 20 | 2018 |
Behrooz ParhamiUniversity of California, Santa BarbaraVerified email at ece.ucsb.edu
