| Optimizing compiler for the cell processor AE Eichenbergert, K O'Brien, K O'Brien, P Wu, T Chen, PH Oden, ... 14th International Conference on Parallel Architectures and Compilation …, 2005 | 260 | 2005 |
| Active memory cube: A processing-in-memory architecture for exascale systems R Nair, SF Antao, C Bertolli, P Bose, JR Brunheroto, T Chen, CY Cher, ... IBM Journal of Research and Development 59 (2/3), 17: 1-17: 14, 2015 | 233 | 2015 |
| Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture AE Eichenberger, JK O'Brien, KM O'Brien, P Wu, T Chen, PH Oden, ... IBM Systems Journal 45 (1), 59-84, 2006 | 224 | 2006 |
| Branch history guided instruction/data prefetching TR Puzak, AM Hartstein, M Charney, DA Prener, PH Oden, V Srinivasan US Patent 6,560,693, 2003 | 145 | 2003 |
| Method and system for transparent dynamic optimization in a multiprocessing environment R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener US Patent 7,146,607, 2006 | 126 | 2006 |
| Approximate computing: Challenges and opportunities A Agrawal, J Choi, K Gopalakrishnan, S Gupta, R Nair, J Oh, DA Prener, ... 2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016 | 123 | 2016 |
| Programming with relaxed synchronization L Renganarayana, V Srinivasan, R Nair, D Prener Proceedings of the 2012 ACM workshop on Relaxing synchronization for …, 2012 | 109 | 2012 |
| Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codes DA Prener US Patent 5,125,092, 1992 | 80 | 1992 |
| Method and system for multiprocessor emulation on a multiprocessor host system ER Altman, R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener, ... US Patent 7,496,494, 2009 | 78 | 2009 |
| Method for partitioning programs between a general purpose core and one or more accelerators JKP O'brien, KM O'brien, DA Prener US Patent 9,038,040, 2015 | 65* | 2015 |
| Prefetching using future branch path information derived from branch prediction TR Puzak, AM Hartstein, M Charney, DA Prener, PH Oden US Patent 7,441,110, 2008 | 50 | 2008 |
| Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture E Altman, M Gschwind, D Prener, J Rivers, S Sathaye, JD Wellman, ... US Patent App. 11/047,983, 2006 | 47 | 2006 |
| Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host ER Altman, R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener, ... US Patent 7,953,588, 2011 | 46 | 2011 |
| Method and system for efficient emulation of multiprocessor memory consistency R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener US Patent 9,043,194, 2015 | 42 | 2015 |
| Method and apparatus for reducing latency in set-associative caches using set prediction MJ Charney, PG Emma, DA Prener, TR Puzak US Patent 6,418,525, 2002 | 42 | 2002 |
| Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data JKP O'brien, KM O'brien, DA Prener US Patent 7,962,906, 2011 | 28 | 2011 |
| Hardware execution driven application level derating calculation for soft error rate analysis P Bose, MS Gupta, PN Kudva, DA Prener US Patent 8,949,101, 2015 | 27 | 2015 |
| Method and system for interrupt handling in a multi-processor computer system executing speculative instruction threads CJ Georgiou, DA Prener US Patent 6,032,245, 2000 | 18 | 2000 |
| Hybrid mechanism for more efficient emulation and method therefor R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener US Patent 8,108,843, 2012 | 17 | 2012 |
| Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry BM Fleischer, TW Fox, HM Jacobson, JH Moreno, R Nair, DA Prener US Patent 9,632,777, 2017 | 15 | 2017 |
