| Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and TSVs MO Hossen, B Chava, G Van der Plas, E Beyne, MS Bakir IEEE Transactions on Electron Devices 67 (1), 11-17, 2019 | 34 | 2019 |
| Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor SUZ Khan, MS Hossain, FU Rahman, R Zaman, MO Hossen, ... International Journal of Numerical Modelling: Electronic Networks, Devices …, 2015 | 17 | 2015 |
| Beol-embedded 3d polylithic integration: Thermal and interconnection considerations A Kaul, SK Rajan, MO Hossen, GS May, MS Bakir 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 1459-1467, 2020 | 14 | 2020 |
| Power delivery network modeling and benchmarking for emerging heterogeneous integration technologies Y Zhang, MO Hossen, MS Bakir IEEE Transactions on Components, Packaging and Manufacturing Technology 9 (9 …, 2019 | 14 | 2019 |
| Compact transient thermal model of microfluidically cooled three-dimensional stacked chips with pin-fin enhanced microgap Y Hu, MO Hossen, Z Wan, MS Bakir, Y Joshi Journal of Electronic Packaging 143 (3), 031007, 2021 | 10 | 2021 |
| Power delivery network benchmarking for interposer and bridge-chip-based 2.5-D integration Y Zhang, MO Hossen, MS Bakir IEEE Electron Device Letters 39 (1), 99-102, 2017 | 10 | 2017 |
| Analytical modeling of gate capacitance and drain current of gate-all-around InxGa1−xAs nanowire MOSFET SUZ Khan, MS Hossain, MO Hossen, FU Rahman, R Zaman, ... 2014 2nd International Conference on Electronic Design (ICED), 89-93, 2014 | 10 | 2014 |
| Thermomechanical analysis and package-level optimization of mechanically flexible interconnects for interposer-on-motherboard assembly MO Hossen, JL Gonzalez, MS Bakir IEEE Transactions on Components, Packaging and Manufacturing Technology 8 …, 2018 | 7 | 2018 |
| Capacitance-voltage characteristics of gate-all-around InxGa1-xAs nanowire transistor QDM Khosru, SUZ Khan, MS Hossain, FU Rahman, MO Hossen, ... ECS Transactions 53 (1), 169, 2013 | 6 | 2013 |
| Thermal-power delivery network co-analysis for multi-die integration MO Hossen, Y Zhang, MS Bakir 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging …, 2018 | 5 | 2018 |
| Heterogeneous multi-die stitching: Technology demonstration and design considerations PK Jo, MO Hossen, X Zhang, Y Zhang, MS Bakir 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 1512-1518, 2018 | 4 | 2018 |
| Uncoupled mode space approach towards transport modeling of Gate-All-Around InxGa1−xAs nanowire MOSFET SUZ Khan, MS Hossain, FU Rahman, R Zaman, MO Hossen, ... 8th International Conference on Electrical and Computer Engineering, 100-103, 2014 | 4 | 2014 |
| Self-consistent determination of threshold voltage of In-rich Gate-All-Around InxGa1−xAs nanowire transistor incorporating quantum mechanical effect R Zaman, SUZ Khan, MS Hossain, FU Rahman, MO Hossen, ... 2012 7th International Conference on Electrical and Computer Engineering …, 2012 | 3 | 2012 |
| Analysis of power delivery network (pdn) in bridge-chips for 2.5-d heterogeneous integration MO Hossen, A Kaul, E Nurvitadhi, MD Pant, R Gutala, A Dasu, MS Bakir IEEE Transactions on Components, Packaging and Manufacturing Technology 12 …, 2022 | 2 | 2022 |
| Ballistic performance limit and gate leakage modeling of Rectangular Gate-all-around InGaAs Nanowire Transistors with ALD Al2O3 as Gate Dielectric MO Hossen, MS Hossain, SUZ Khan, FU Rahman, R Zaman, ... 2012 IEEE International Conference on Electron Devices and Solid State …, 2012 | 2 | 2012 |
| Design Space Exploration of Power Delivery For Advanced Packaging Technologies MO Hossen, Y Zhang, H Fathi Moghadam, Y Zhang, M Dayringer, ... https://arxiv.org/abs/2008.03124, 2020 | 1 | 2020 |
| Self-consistent capacitance-voltage characterization of gate-all-around graded nanowire transistor SUZ Khan, MS Hossain, MO Hossen, FU Rahman, R Zaman, ... arXiv preprint arXiv:1406.5257, 2014 | 1 | 2014 |
| Analytical modeling of potential profile and threshold voltage for rectangular gate-all-around III–V nanowire MOSFETs with ATLAS verification MS Hossain, SUZ Khan, MO Hossen, FU Rahman, R Zaman, ... 2012 IEEE International Conference on Electron Devices and Solid State …, 2012 | 1 | 2012 |
| Design Considerations for Power Delivery Network and Metal-Insulator-Metal Capacitor Integration in Bridge-Chips for 2.5-D Heterogeneous Integration A Kaul, MO Hossen, M Manley, MS Bakir 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), 985-990, 2023 | | 2023 |
| Power Delivery and Thermal Considerations for 2.5-D and 3-D Integration Technologies MO Hossen Georgia Institute of Technology, 2019 | | 2019 |
Quazi D. M. KhosruBangladesh University of Engineering and TechnologyVerified email at eee.buet.ac.bd
